Patents by Inventor Cheng-Che Lee
Cheng-Che Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240177893Abstract: An over-current protection device includes a heat-sensitive layer and an electrode layer. The electrode layer includes a top metal layer and a bottom metal layer, and the heat-sensitive layer attached therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a conductive filler. The polymer matrix includes a polyolefin-based homopolymer and a polyolefin-based copolymer. The polyolefin-based homopolymer has a first coefficient of thermal expansion (CTE), and the polyolefin-based copolymer has a second CTE lower than the first CTE. The polyolefin-based homopolymer and the polyolefin-based copolymer together form an interpenetrating polymer network (IPN).Type: ApplicationFiled: May 3, 2023Publication date: May 30, 2024Inventors: CHENG-YU TUNG, Chia-Yuan Lee, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, Yao-Te Chang, FU-HUA CHU, Takashi Hasunuma
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Patent number: 11990258Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, a conductive filler, and a titanium-containing dielectric filler. The polymer matrix has a fluoropolymer. The titanium-containing dielectric filler has a compound represented by a general formula of MTiO3, wherein the M represents transition metal or alkaline earth metal. The total volume of the PTC material layer is calculated as 100%, and the titanium-containing dielectric filler accounts to for 5-15% by volume of the PTC material layer.Type: GrantFiled: September 28, 2022Date of Patent: May 21, 2024Assignee: POLYTRONICS TECHNOLOGY CORP.Inventors: Hsiu-Che Yen, Yung-Hsien Chang, Cheng-Yu Tung, Chen-Nan Liu, Chia-Yuan Lee, Yu-Chieh Fu, Yao-Te Chang, Fu-Hua Chu
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Publication number: 20240145132Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.Type: ApplicationFiled: March 16, 2023Publication date: May 2, 2024Inventors: CHENG-YU TUNG, CHEN-NAN LIU, Chia-Yuan Lee, HSIU-CHE YEN, YUNG-HSIEN CHANG, Yao-Te Chang, FU-HUA CHU
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Publication number: 20240145133Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.Type: ApplicationFiled: April 5, 2023Publication date: May 2, 2024Inventors: CHEN-NAN LIU, YUNG-HSIEN CHANG, CHENG-YU TUNG, HSIU-CHE YEN, Chia-Yuan LEE, Yao-Te CHANG, FU-HUA CHU
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Publication number: 20240127988Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Inventors: HSIU-CHE YEN, YUNG-HSIEN CHANG, CHENG-YU TUNG, Chia-Yuan Lee, CHEN-NAN LIU, Yao-Te Chang, FU-HUA CHU
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Publication number: 20240127989Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.Type: ApplicationFiled: January 25, 2023Publication date: April 18, 2024Inventors: CHIA-YUAN LEE, CHENG-YU TUNG, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, YAO-TE CHANG, FU-HUA CHU
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Patent number: 11949799Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.Type: GrantFiled: April 5, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Che Tsai, Shih-Lien Linus Lu, Cheng Hung Lee, Chia-En Huang
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Publication number: 20240071281Abstract: A display device includes a display panel and a circuit. For a first sub-pixel, the circuit obtains a corresponding second sub-pixel. The circuit calculates a first compensation value according to the grays levels of the first sub-pixel and the second sub-pixel, and calculates a second compensation value according to the polarity states of the first sub-pixel and the second sub-pixel and the difference between the gray levels of the two sub-pixels. The circuit also calculates a gain according to the position of the first sub-pixel, compensates the gray level to the first sub-pixel according to the first compensation value, the second compensation value and the gain to obtain an output gray level, and drives the first sub-pixel according to the output gray level.Type: ApplicationFiled: June 16, 2023Publication date: February 29, 2024Inventors: Cheng-Hsun LEE, Tsai Hsing CHEN, Cheng Che TSAI, Ching-Wen WANG
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Publication number: 20230368028Abstract: Features related to systems and methods for automated generation of a machine learning model based in part on a pretrained model are described. The pretrained model is used as a starting point to augment and retrain according to client specifications. The identification of an appropriate pretrained model is based on the client specifications such as model inputs, model outputs, and similarities between the data used to train the models.Type: ApplicationFiled: July 3, 2023Publication date: November 16, 2023Inventors: Hagay Lupesko, Anirudh Acharya, Cheng-Che Lee, Lai Wei, Kalyanee Chendke, Ankit Khedia, Vandana Kannan, Sandeep Krishnamurthy, Roshani Nagmote
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Patent number: 11769035Abstract: Techniques are described automatically determining runtime configurations used to execute recurrent neural networks (RNNs) for training or inference. One such configuration involves determining whether to execute an RNN in a looped, or “rolled,” execution pattern or in a non-looped, or “unrolled,” execution pattern. Execution of an RNN using a rolled execution pattern generally consumes less memory resources than execution using an unrolled execution pattern, whereas execution of an RNN using an unrolled execution pattern typically executes faster. The configuration choice thus involves a time-memory tradeoff that can significantly affect the performance of the RNN execution. This determination is made automatically by a machine learning (ML) runtime by analyzing various factors such as, for example, a type of RNN being executed, the network structure of the RNN, characteristics of the input data to the RNN, an amount of computing resources available, and so forth.Type: GrantFiled: December 13, 2018Date of Patent: September 26, 2023Assignee: Amazon Technologies, Inc.Inventors: Lai Wei, Hagay Lupesko, Anirudh Acharya, Ankit Khedia, Sandeep Krishnamurthy, Cheng-Che Lee, Kalyanee Shriram Chendke, Vandana Kannan, Roshani Nagmote
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Patent number: 11495492Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.Type: GrantFiled: September 9, 2020Date of Patent: November 8, 2022Assignee: Winbond Electronics Corp.Inventor: Cheng-Che Lee
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Publication number: 20220157611Abstract: The present disclosure provides a semiconductor sensing device. The semiconductor sensing device includes a substrate having a sensing region. The sensing region includes an active feature. The active feature includes an anchor portion, an elevated portion, and a nanowire portion. The anchor portion is on a top surface of the substrate. The elevated portion is spaced from the top surface of the substrate by a vertical distance and connected to the anchor portion. The nanowire portion is on the top surface of the substrate and connected to the anchor portion. The vertical distance is greater than or equal to a thickness of the nanowire portion.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Inventors: Cheng-Che LEE, Lin-Chien CHEN
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Patent number: 11289336Abstract: Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed.Type: GrantFiled: January 7, 2020Date of Patent: March 29, 2022Assignee: Helios Bioelectronics Inc.Inventors: Cheng-Che Lee, Lin-Chien Chen
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Publication number: 20210265197Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.Type: ApplicationFiled: September 9, 2020Publication date: August 26, 2021Applicant: Winbond Electronics Corp.Inventor: Cheng-Che Lee
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Publication number: 20200234967Abstract: Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed.Type: ApplicationFiled: January 7, 2020Publication date: July 23, 2020Inventors: Cheng-Che LEE, Lin-Chien CHEN
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Publication number: 20200033287Abstract: The method of operation of a meter includes placing a sample on a test strip, assigning a first electrode of the test strip to be a counter electrode, applying a first signal to the test strip during a first period of time, assigning a second electrode of the test strip to be the counter electrode, applying a second signal to the test strip to measure the concentration of an analyte in the sample.Type: ApplicationFiled: October 2, 2019Publication date: January 30, 2020Inventors: Wen-Huang Chen, Cheng-Che Lee
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Publication number: 20190056345Abstract: The method of operation of a meter includes placing a sample on a test strip, assigning a first electrode of the test strip to be a counter electrode, applying a first signal to the test strip during a first period of time, assigning a second electrode of the test strip to be the counter electrode, applying a second signal to the test strip to measure the concentration of an analyte in the sample.Type: ApplicationFiled: August 16, 2017Publication date: February 21, 2019Inventors: Wen-Huang Chen, Cheng-Che Lee
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Publication number: 20170016845Abstract: A test strip includes a substrate, a spacer layer having a notch, a reagent layer, a support layer, and a cover layer having a covering portion covering the notch and a channel portion extending rearward from the covering portion corresponding to a rear end of the notch. The substrate is attached under the spacer layer and has a reaction region exposed from the notch. The support layer is located at two sides of the notch and connected to the cover layer and the spacer layer to make the channel portion away from the spacer layer at a vertical distance. The support layer, the covering portion, the notch, and the substrate form a reaction chamber for allowing an analyte solution to react with the reagent layer coated on the reaction region, and the support layer, the channel portion, and the spacer layer forms a channel for exhausting air.Type: ApplicationFiled: July 4, 2016Publication date: January 19, 2017Inventors: Cheng-Che Lee, Han-Ching Tsai, Cheng-Yun Hsiao, Jen-Hao Liu
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Publication number: 20140174948Abstract: A method of a test strip detecting concentration of an analyte of a sample includes placing the sample in a reaction region of the test strip, wherein the analyte reacts with an enzyme to generate a plurality of electrons, and the plurality of electrons are transferred to a working electrode of the reaction region through a mediator; applying an electrical signal to the working electrode; measuring a first current through the working electrode during a first period; the mediator generating an intermediate according to the electrical signal during a second period; measuring a second current through the working electrode during a third period; calculating initial concentration of the analyte according to the first current; calculating a diffusion factor of the intermediate in the sample according to the second current; and correcting the initial concentration to generate new concentration of the analyte according to the diffusion factor.Type: ApplicationFiled: December 22, 2013Publication date: June 26, 2014Applicant: TYSON BIORESEARCH INC.Inventors: Cheng-Che Lee, Wen-Huang Chen, Han-Ching Tsai, Chen-Yu Yang
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Patent number: 8505819Abstract: The present invention discloses a biological measuring device with auto coding capabilities. In accordance with one embodiment of the present invention, the biological measuring device with auto coding capabilities includes a test strip having a substrate and at least a first contact pad and a second contact pad provided on the substrate; and a code reader having at least a first metal pin and a second metal pin to couple to the first contact pad and the second contact pad to obtain coding information associated with the test strip, wherein the code reader is capable of reading the coding information based on a movement of the test strip before the test strip is placed still in relation to the code reader for a proper reading of a sample.Type: GrantFiled: October 26, 2011Date of Patent: August 13, 2013Assignee: Tyson Bioresearch, Inc.Inventors: Cheng-Che Lee, Wen-Hai Tsai, Keng-Hao Chang, Chiu-Chin Yang, Waken Chen, Jih-Hsin Yeh