Patents by Inventor Cheng-chieh Hsieh
Cheng-chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230065941Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.Type: ApplicationFiled: August 29, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
-
Publication number: 20230060720Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
-
Patent number: 11594520Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.Type: GrantFiled: October 19, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
-
Patent number: 11587883Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.Type: GrantFiled: February 1, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
-
Publication number: 20230018511Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
-
Patent number: 11532596Abstract: A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component.Type: GrantFiled: March 5, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
-
Patent number: 11527502Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.Type: GrantFiled: February 22, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
-
Patent number: 11521959Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.Type: GrantFiled: July 9, 2020Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
-
Publication number: 20220382004Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo
-
Patent number: 11506843Abstract: A semiconductor device including a singulated structure and an optical fiber assembly is provided. The singulated structure includes a photonic die, an electronic die connected to the photonic die and an optical element over the photonic die. The optical fiber assembly is disposed on a top of the singulated structure and includes a holder and an optical fiber structure. The holder keeps an air gap from the optical element. The optical fiber structure is carried by the holder and configured to be optically communicated with the photonic die through the optical element.Type: GrantFiled: May 13, 2021Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Che-Hsiang Hsu, Chewn-Pu Jou, Feng-Wei Kuo, Min-Hsiang Hsu
-
Publication number: 20220365286Abstract: A semiconductor device including a singulated structure and an optical fiber assembly is provided. The singulated structure includes a photonic die, an electronic die connected to the photonic die and an optical element over the photonic die. The optical fiber assembly is disposed on a top of the singulated structure and includes a holder and an optical fiber structure. The holder keeps an air gap from the optical element. The optical fiber structure is carried by the holder and configured to be optically communicated with the photonic die through the optical element.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Che-Hsiang Hsu, Chewn-Pu Jou, Feng-Wei Kuo, Min-Hsiang Hsu
-
Publication number: 20220365273Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
-
Publication number: 20220365297Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: ApplicationFiled: May 14, 2021Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
-
Publication number: 20220359488Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
-
Publication number: 20220352078Abstract: A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hung Tseng, Cheng-Chieh Hsieh, Hao-Yi Tsai
-
Publication number: 20220299719Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
-
Publication number: 20220285317Abstract: A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
-
Patent number: 11410932Abstract: A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.Type: GrantFiled: March 30, 2020Date of Patent: August 9, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hung Tseng, Cheng-Chieh Hsieh, Hao-Yi Tsai
-
Publication number: 20220165675Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
-
Patent number: 11251119Abstract: A package structure includes a first semiconductor die, an insulating encapsulant, a plurality of first through insulator vias, a plurality of second through insulator vias, and a redistribution layer. The insulating encapsulant is encapsulating the first semiconductor die. The first through insulator vias are located in a central area of the insulating encapsulant surrounding the first semiconductor die. The second through insulator vias are located in a peripheral area of the insulating encapsulant surrounding the plurality of first through insulator vias located in the central area, wherein an aspect ratio of the plurality of second through insulator vias is greater than an aspect ratio of the plurality of first through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the first semiconductor die, the plurality of first through insulator vias and the plurality of second through insulator vias.Type: GrantFiled: January 21, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Cheng-Chieh Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng