Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Abstract: A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.