Patents by Inventor Cheng-Chieh Wu
Cheng-Chieh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170506Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
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Publication number: 20240170343Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: ApplicationFiled: January 24, 2024Publication date: May 23, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
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Publication number: 20240113143Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.Type: ApplicationFiled: January 6, 2023Publication date: April 4, 2024Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Publication number: 20240105778Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: I-Sheng CHEN, Yee-Chia YEO, Chih Chieh YEH, Cheng-Hsien WU
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Publication number: 20240088182Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
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Patent number: 11923386Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.Type: GrantFiled: April 24, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
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Patent number: 11923252Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 27, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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Publication number: 20240063075Abstract: A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pavithra Sriram, Kuo-Lung Pan, Po-Yuan Teng, Cheng-Chieh Wu, Mao-Yen Chang, Yu-Chia Lai, Shu-Rong Chun, Hao-Yi Tsai
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Publication number: 20240019486Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.Type: ApplicationFiled: January 9, 2023Publication date: January 18, 2024Inventors: Cheng-Chieh Wu, Kuo-Lung Pan, Shu-Rong Chun, Hao-Yi Tsai, Po-Yuan Teng, Mao-Yen Chang, Cheng Yu Liu, Chia-Wen Lin
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Publication number: 20230326766Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.Type: ApplicationFiled: June 9, 2023Publication date: October 12, 2023Inventors: JEN-FU LIU, MING HUNG TSENG, YEN-LIANG LIN, LI-KO YEH, HUI-CHUN CHIANG, CHENG-CHIEH WU
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Patent number: 11715646Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.Type: GrantFiled: July 16, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jen-Fu Liu, Ming Hung Tseng, Yen-Liang Lin, Li-Ko Yeh, Hui-Chun Chiang, Cheng-Chieh Wu
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Publication number: 20230015970Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: JEN-FU LIU, MING HUNG TSENG, YEN-LIANG LIN, LI-KO YEH, HUI-CHUN CHIANG, CHENG-CHIEH WU
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Publication number: 20220415737Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chieh Wu, Ting Hao Kuo, Kuo-Lung Pan, Po-Yuan Teng, Yu-Chia Lai, Shu-Rong Chun, Mao-Yen Chang, Wei-Kang Hsieh, Pavithra Sriram, Hao-Yi Tsai, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 10762699Abstract: A machining parameter automatic generation system includes a geometric data capturing module, a feature recognition learning network and a machining parameter learning network. The geometric data capturing module captures a geometric shape of a workpiece to generate a candidate feature list. The feature recognition learning network trains the candidate feature list according to a first neural network model to obtain an applicable feature list. The machining parameter learning network trains the applicable feature list and the candidate machining parameter according to a second neural network model to obtain an applicable machining parameter. The applicable machining parameter is used to generate a machining program, and the machining program is read by a machine tool for processing.Type: GrantFiled: December 19, 2018Date of Patent: September 1, 2020Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yang-Lun Liu, Yu-Lin Tsai, Yao-Yang Tsai, Cheng-Chieh Wu, Shuo-Peng Liang
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Publication number: 20200184720Abstract: A machining parameter automatic generation system includes a geometric data capturing module, a feature recognition learning network and a machining parameter learning network. The geometric data capturing module captures a geometric shape of a workpiece to generate a candidate feature list. The feature recognition learning network trains the candidate feature list according to a first neural network model to obtain an applicable feature list. The machining parameter learning network trains the applicable feature list and the candidate machining parameter according to a second neural network model to obtain an applicable machining parameter. The applicable machining parameter is used to generate a machining program, and the machining program is read by a machine tool for processing.Type: ApplicationFiled: December 19, 2018Publication date: June 11, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yang-Lun LIU, Yu-Lin TSAI, Yao-Yang TSAI, Cheng-Chieh WU, Shuo-Peng LIANG
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Patent number: 9748183Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.Type: GrantFiled: March 10, 2017Date of Patent: August 29, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ching-Wen Chiang, Cheng-Hao Ciou, Cheng-Chieh Wu, Kuang-Hsin Chen, Hsien-Wen Chen
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Publication number: 20170186703Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.Type: ApplicationFiled: March 10, 2017Publication date: June 29, 2017Inventors: Ching-Wen Chiang, Cheng-Hao Ciou, Cheng-Chieh Wu, Kuang-Hsin Chen, Hsien-Wen Chen
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Patent number: 9627307Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.Type: GrantFiled: October 22, 2015Date of Patent: April 18, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ching-Wen Chiang, Cheng-Hao Ciou, Cheng-Chieh Wu, Kuang-Hsin Chen, Hsien-Wen Chen
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Publication number: 20160133556Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.Type: ApplicationFiled: October 22, 2015Publication date: May 12, 2016Inventors: Ching-Wen Chiang, Cheng-Hao Ciou, Cheng-Chieh Wu, Kuang-Hsin Chen, Hsien-Wen Chen