Patents by Inventor Cheng-Ching Huang
Cheng-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186704Abstract: A circular polarized antenna array module and a wireless communication device, including a plurality of circular polarized transmitting antennas and circular polarized receiving antennas, a dielectric substrate, and a plurality of first group of phase shifting units and second group of phase shifting units. In each row of the circular polarized transmitting/receiving antennas, every two adjacent circular polarized transmitting/receiving antennas arranged with a distance, each of the circular polarized transmitting antennas arranged with a first feed point and a second feed point, each of the circular polarized receiving antennas arranged with a third feed point and a fourth feed point. Each row of the circular polarized transmitting antennas and each row of the circular polarized receiving antennas alternately placed to form array arranged on the dielectric substrate.Type: ApplicationFiled: August 29, 2023Publication date: June 6, 2024Applicant: Chiun Mai Communication Systems, Inc.Inventors: CHENG-AN CHEN, CHIA-HUNG SU, CHANG-CHING HUANG, LUNG-TA CHANG, SHU-WEI JHANG
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Patent number: 12002750Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.Type: GrantFiled: January 7, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
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Patent number: 11993066Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: GrantFiled: August 5, 2021Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Patent number: 11990400Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.Type: GrantFiled: June 1, 2022Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Ya Lo, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee
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Publication number: 20240136221Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
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Patent number: 11951637Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.Type: GrantFiled: June 4, 2021Date of Patent: April 9, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Cheng-Hao Huang, Shi-Yu Wang, Po-Chiao Huang, Han-Ching Lin, Meng-Zong Li
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 11942130Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.Type: GrantFiled: March 23, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
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Patent number: 11935783Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.Type: GrantFiled: May 16, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
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Patent number: 11630153Abstract: A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.Type: GrantFiled: April 26, 2021Date of Patent: April 18, 2023Assignee: Winbond Electronics Corp.Inventors: Chih-Chiang Lai, Cheng-Ching Huang
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Publication number: 20220341991Abstract: A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Applicant: Winbond Electronics Corp.Inventors: Chih-Chiang Lai, Cheng-Ching Huang
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Patent number: 7363217Abstract: A method for analyzing energy consistency to process data, for use with an electronic apparatus, includes the steps of analyzing energy consistency to process data, performing a data-buffering process for outputting a data frame, performing a data-processing process for outputting a shaping residual after inputting the data frame, performing an energy-framing process for dividing the shaping residual into N sub-blocks after inputting the shaping residual to calculate energy of N sub-blocks to get a plurality of energy coefficients, performing a consistency-checking process for inputting the energy coefficients to check whether the energy coefficients can fulfill a threshold screening for consistency, enerating the decision about the data frame which should be processed by the long-type window coding if the spectral characteristics are consistent wherein the energy coefficients conform to the consistent energy relationship, and generating the decision about the data frame should be processed by the short-typeType: GrantFiled: August 27, 2004Date of Patent: April 22, 2008Assignee: Vivotek, Inc.Inventors: Yan-Chen Lu, Cheng-Ching Huang
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Publication number: 20050228839Abstract: A method for analyzing energy consistency to process data, for use with an electronic apparatus, includes the steps of analyzing energy consistency to process data, performing a data-buffering process for outputting a data frame, performing a data-processing process for outputting a shaping residual after inputting the data frame, performing an energy-framing process for dividing the shaping residual into N sub-blocks after inputting the shaping residual to calculate energy of N sub-blocks to get a plurality of energy coefficients, performing a consistency-checking process for inputting the energy coefficients to check whether the energy coefficients can fulfill a threshold screening for consistency, enerating the decision about the data frame which should be processed by the long-type window coding if the spectral characteristics are consistent wherein the energy coefficients conform to the consistent energy relationship, and generating the decision about the data frame should be processed by the short-typeType: ApplicationFiled: August 27, 2004Publication date: October 13, 2005Inventors: Yan-Chen Lu, Cheng-Ching Huang
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Publication number: 20050153054Abstract: A method for manufacturing a multicolored three-dimensional candy has the steps of heating materials, mixing pigment with the heated materials, injecting the mixed materials into a mold, adding a supplementary material to the mold, cooling to form a product and releasing the product from the mold. Since the materials are divided in parts into inject into different areas of the mold, the multicolored three-dimensional candy manufactured by the method has different areas with different depths, contours, shapes and colors. The appearance of the candy can attract customers to buy it.Type: ApplicationFiled: January 9, 2004Publication date: July 14, 2005Inventors: Cheng-Lung Huang, Cheng-Ching Huang, Chun-Hsien Wang
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Publication number: 20030234338Abstract: A mold for making confections mainly includes a main body made of a flexible material and provided at one surface with a recess. The recess may show different shapes and is provided on an inner bottom surface with raised and depressed portions matching with the shape of the recess, dams lower than a top of the recess to divide the recess into several separated areas, and fine engraving ribs lower than the dams to show different curves or straight lines. Materials of different colors are separately poured into the separated areas in the recess to a level lower than the dams, and a binding stratum is formed between tops of the dams and the recess. After the materials and the binding stratum are set to form a molded confection, the main body is inverted and bent upward to separate the molded confection from the mold.Type: ApplicationFiled: June 19, 2002Publication date: December 25, 2003Inventors: Cheng-Lung Huang, Cheng-Ching Huang, Chun-Hsien Wang
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Patent number: D1024052Type: GrantFiled: February 14, 2022Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Cheng-Han Lin, Pao-Ching Huang
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Patent number: D1024055Type: GrantFiled: February 14, 2022Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Hsueh-Wei Chung, Pao-Ching Huang, Cheng-Han Lin
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Patent number: D1025980Type: GrantFiled: February 14, 2022Date of Patent: May 7, 2024Assignee: Acer IncorporatedInventors: Cheng-Han Lin, Pao-Ching Huang, Hsueh-Wei Chung