Abstract: Boot firmware for a computing device can be modularly and dynamically composed to facilitate implementing changes and updates to a computing device's firmware. The firmware image can include a primary module, which is responsible for certain basic initializations, and a module list, which can include a listing of additional modules that are to be executed during the boot procedure. The module list can be used to identify and access the selected modules from a module library, such as via globally unique identifiers (GUIDs). Once acquired, the selected modules can be executed, taking into account required dependency modules (whether included in the selected modules or not) and configuration settings. The module library can be stored entirely locally (e.g., as part of a distributed firmware image), entirely remotely (e.g., accessible via network connection), or a mixture of locally and remotely.

Abstract: An e-paper identification card system including an e-paper identification card and a data updating apparatus is provided. The e-paper identification card is configured to display first image information. The data updating apparatus is electrically connected to the e-paper identification card. The data updating apparatus is configured to update the e-paper identification card according to the first image information to drive the e-paper identification card to display second image information. In addition, an e-paper identification card is also provided.

Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A method, computer program product, and computer system for public speaking guidance is provided. A processor retrieves speaker data regarding a speech made by a user. A processor separates the speaker data into one or more speaker modalities. A processor extracts one or more speaker features from the speaker data for the one or more speaker modalities. A processor generates a performance classification based on the one or more speaker features. A processor sends to the user guidance regarding the speech based on the performance classification.

Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.

Abstract: The present disclosure provides intelligent radio frequency interference mitigation in a computing platform. The computing platform includes a processor, a memory, a system clock and a wireless network interface. The system clock can be controlled so that the processor and/or the memory may operate at a slow frequency or a fast frequency. The wireless network may operate on a radio channel that experiences radio frequency interference at the fast frequency. The system clock may be intelligently controlled to select the slow frequency to reduce radio frequency interference to prioritize execution of a network application, or to select the fast frequency to increase processor speed and prioritize execution of a local application.

Abstract: An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A vestibular system examination device includes a platform unit and an examination unit. The platform unit includes a base, a driving mechanism mounted to the base, and a seat mounted to the driving mechanism and adapted for a user to sit thereon. The seat is driven movably and rotatably with six degrees of freedom by the driving mechanism. The examining unit includes a detector adapted for detecting eye movement or electrooculography of the user, a measuring module electrically connected to the platform unit for measuring location and displacement thereof, and a processing module electrically connected to the detector and the measuring module for receiving and processing data acquired from the detector and the measuring module.

Abstract: A server system and a power-saving method thereof are provided. The power-saving method includes: enabling, by a programmable logic unit in a working mode, a power-on control unit to operate according to a working power; determining, by the power-on control unit in the working mode, whether a power-saving power-off signal is received, and when the power-saving power-off signal is received, controlling, by the power-on control unit, the server system to be powered off and switched from the working mode to a soft-off mode; operating, by the programmable logic unit, according to standby power to enable, in the soft-off mode, the power-on control unit to operate according to the standby power; and turning off, by a baseboard management control unit, the programmable logic unit according to the power-saving power-off signal when the power-on control unit operates according to the standby power, to turn off the power-on control unit.

Abstract: A server system and a power-saving method thereof are provided. The power-saving method includes: enabling, by a programmable logic unit in a working mode, a power-on control unit to operate according to a working power; determining, by the power-on control unit in the working mode, whether a power-saving power-off signal is received, and when the power-saving power-off signal is received, controlling, by the power-on control unit, the server system to be powered off and switched from the working mode to a soft-off mode; operating, by the programmable logic unit, according to standby power to enable, in the soft-off mode, the power-on control unit to operate according to the standby power; and turning off, by a baseboard management control unit, the programmable logic unit according to the power-saving power-off signal when the power-on control unit operates according to the standby power, to turn off the power-on control unit.

Abstract: A vestibular system examination device includes a platform unit and an examination unit. The platform unit includes abase, a driving mechanism mounted to the base, and a seat mounted to the driving mechanism and adapted for a user to sit thereon. The seat is driven movably and rotatably with six degrees of freedom by the driving mechanism. The examining unit includes a detector adapted for detecting eye movement or electrooculography of the user, a measuring module electrically connected to the platform unit for measuring location and displacement thereof, and a processing module electrically connected to the detector and the measuring module for receiving and processing data acquired from the detector and the measuring module.