Patents by Inventor Cheng-Guan Yuan
Cheng-Guan Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10361272Abstract: An InGaAlP Schottky field effect transistor with AlGaAs carrier supply layer comprises a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer and a cap layer sequentially formed on a compound semiconductor substrate; the cap layer has a gate recess, a bottom of the gate recess is defined by the Schottky barrier layer; a source electrode and a drain electrode are formed respectively on the cap layer at two sides with respect to the gate recess, the source electrode and the drain electrode form respectively an ohmic contact with the cap layer; a gate electrode is formed on the Schottky barrier layer within the gate recess, the gate electrode and the Schottky barrier layer form a Schottky contact; wherein the carrier supply layer is made of AlGaAs; the Schottky barrier layer is made of InGaAlP.Type: GrantFiled: October 30, 2017Date of Patent: July 23, 2019Assignee: Win Semiconductors Corp.Inventors: Shih-Ming Joseph Liu, Yu-Chi Wang, Cheng-Guan Yuan, Hsi-Tsung Lin, Chia Hsiung Lee
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Publication number: 20190074356Abstract: An InGaAlP Schottky field effect transistor with AlGaAs carrier supply layer comprises a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer and a cap layer sequentially formed on a compound semiconductor substrate; the cap layer has a gate recess, a bottom of the gate recess is defined by the Schottky barrier layer; a source electrode and a drain electrode are formed respectively on the cap layer at two sides with respect to the gate recess, the source electrode and the drain electrode form respectively an ohmic contact with the cap layer; a gate electrode is formed on the Schottky barrier layer within the gate recess, the gate electrode and the Schottky barrier layer form a Schottky contact; wherein the carrier supply layer is made of AlGaAs; the Schottky barrier layer is made of InGaAlP.Type: ApplicationFiled: October 30, 2017Publication date: March 7, 2019Inventors: Shih-Ming Joseph LIU, Yu-Chi WANG, Cheng-Guan YUAN, Hsi-Tsung LIN, Chia Hsiung LEE
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Patent number: 10186620Abstract: An InGaAlP Schottky field effect transistor with stepped bandgap ohmic contact, comprising: a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer, an intermediate bandgap layer, a cap layer and an ohmic metal layer sequentially formed on a compound semiconductor substrate; wherein the Schottky barrier layer is made of InGaAlP; the ohmic metal layer and the cap layer form an ohmic contact. The Schottky barrier layer, the intermediate bandgap layer and the cap layer have a Schottky-barrier-layer bandgap, an intermediate bandgap and a cap-layer bandgap respectively, wherein the intermediate bandgap is less than the Schottky-barrier-layer bandgap and greater than the cap-layer bandgap.Type: GrantFiled: October 30, 2017Date of Patent: January 22, 2019Assignee: WIN SEMICONDUCTOR CORP.Inventors: Cheng-Guan Yuan, Shih-Ming Joseph Liu, Hsi-Tsung Lin, Chia Hsiung Lee
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Patent number: 9064704Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.Type: GrantFiled: February 15, 2013Date of Patent: June 23, 2015Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chih-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Patent number: 8987781Abstract: An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer.Type: GrantFiled: April 7, 2011Date of Patent: March 24, 2015Assignee: Win Semiconductors Corp.Inventors: Cheng-Guan Yuan, Shih-Ming Liu
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Patent number: 8970998Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: GrantFiled: December 31, 2012Date of Patent: March 3, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Patent number: 8964342Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resistor, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: GrantFiled: December 31, 2012Date of Patent: February 24, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Publication number: 20140231875Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chih-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140183609Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resister, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140183544Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Patent number: 8653562Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.Type: GrantFiled: December 28, 2011Date of Patent: February 18, 2014Assignee: WIN Semiconductor Corp.Inventors: Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Publication number: 20130082305Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.Type: ApplicationFiled: December 28, 2011Publication date: April 4, 2013Inventors: Cheng-Guan YUAN, Shih-Ming Joseph Liu
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Publication number: 20120091507Abstract: An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer.Type: ApplicationFiled: April 7, 2011Publication date: April 19, 2012Inventors: Cheng-Guan Yuan, Shih-Ming Liu
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Publication number: 20100171179Abstract: A full periphery multi-gate transistor with ohmic strip is disclosed. The multi-gate transistor comprises a substrate, a multi-layer structure, a source finger, a drain finger, and a gate. The gate is formed between the source finger and the drain finger, and then a conduction channel is formed between the source finger and the drain finger. The gate also meanderingly wraps around an end of the source finger and an end of the drain finger. Therefore, the end of the source finger and the end of the drain finger are parts of the conduction channel and both provide channel conductance. In addition, an ohmic strip is formed between two gate lines of the gate.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shih Ming LIU, Cheng Guan YUAN
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Publication number: 20090278171Abstract: A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap layer between the source region and the drain region. A source electrode and a drain electrode are respectively formed on the source region and the drain region, and a gate electrode is formed on the gate region, wherein the source region and the drain region of the cap layer are respectively provided with an opening for forming a good ohmic contact between the source region and the drain region with the channel layer respectively.Type: ApplicationFiled: May 9, 2008Publication date: November 12, 2009Applicant: WIN Semiconductors Corp.Inventors: Iris Hsieh, Jeff Yeh, Cheng-Guan Yuan, Yu Chi Wang