Patents by Inventor Cheng-Hao Chen

Cheng-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363396
    Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Patent number: 12125852
    Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240346351
    Abstract: The disclosure provides a quantum device and a microwave device. The quantum device includes a first partition, a second partition, an upper circuit board, a lower circuit board and a flexible circuit. The second partition is arranged below the first partition. The first partition and the second partition are used to define an ultra-low temperature chamber of the quantum device. The upper circuit board, the lower circuit board and the flexible circuit are arranged in the ultra-low temperature chamber. The upper circuit board is disposed on a lower surface of the first partition. The lower circuit board is disposed on an upper surface of the second partition. The flexible circuit is electrically connected between the upper circuit board and the lower circuit board to provide multiple signal paths for mutual signal transmission between the upper circuit board and the lower circuit board.
    Type: Application
    Filed: December 27, 2022
    Publication date: October 17, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chang-Sheng Chen, Che-Hao Li, Cheng-Hua Tsai, Meng-Hsuan Chen, Wei Chaun Yu, Meng-Sheng Chen
  • Publication number: 20240345941
    Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).
    Type: Application
    Filed: May 2, 2023
    Publication date: October 17, 2024
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Jianguo Ren, Hung-Yu Chiou, Cheng-Tien Wan, Chao-Yang Yeh, Wei-Lien Chen, Man-Yun Su, Zemin Xu, Wen-Hao Hsueh, Wei-Chuan Liu
  • Publication number: 20240347389
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. A bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Lo-Heng CHANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240347625
    Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Publication number: 20240347606
    Abstract: Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Pei Ying LAI, Cheng-Chieh LIN, Hsueh-Ju CHEN, Tsung-Da LIN, Cheng-Hao HOU, Chi On CHUI
  • Patent number: 12119887
    Abstract: The present disclosure provides intelligent radio frequency interference mitigation in a computing platform. The computing platform includes a processor, a memory, a system clock and a wireless network interface. The system clock can be controlled so that the processor and/or the memory may operate at a slow frequency or a fast frequency. The wireless network may operate on a radio channel that experiences radio frequency interference at the fast frequency. The system clock may be intelligently controlled to select the slow frequency to reduce radio frequency interference to prioritize execution of a network application, or to select the fast frequency to increase processor speed and prioritize execution of a local application.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: October 15, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ruei-Ting Lin, Cheng-Fang Lin, Huai-yung Yen, Ren-Hao Chen, Lo-Chun Tung
  • Publication number: 20240339524
    Abstract: A method includes forming a fin protruding from a substrate; forming a gate structure extending over the fin; forming a source/drain region in the fin adjacent the gate structure; forming a first isolation region over the source/drain region; forming a first mask layer over the gate structure; etching the first isolation region using the first mask layer as an etch mask to form a first recess; conformally depositing a second mask layer over the first mask layer and within the first recess; depositing a third mask layer over the second mask layer; etching the third mask layer, the second mask layer, and the first isolation region to form a second recess that exposes the source./drain region; and depositing a conductive material in the second recess.
    Type: Application
    Filed: July 18, 2023
    Publication date: October 10, 2024
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Chun-Yuan Chen, Sheng-Tsung Wang, Meng-Huan Jao
  • Publication number: 20240332004
    Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing an aluminum nitride layer on the gate dielectric, depositing an aluminum oxide layer on the aluminum nitride layer, performing an annealing process to drive aluminum in the aluminum nitride layer into the gate dielectric, removing the aluminum oxide layer and the aluminum nitride layer, and forming a gate electrode on the gate dielectric.
    Type: Application
    Filed: July 3, 2023
    Publication date: October 3, 2024
    Inventors: Chi On Chui, Cheng-Hao Hou, Da-Yuan Lee, Pei Ying Lai, Yi Hsuan Chen, Jia-Yun Xu
  • Patent number: 12107011
    Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Li-Zhen Yu, Huan-Chieh Su, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240322098
    Abstract: An electronic device includes a temporary storage base, an adhesive layer, light-emitting elements, and a sealant. The adhesive layer is disposed on the temporary storage base. The light-emitting elements are disposed on the adhesive layer. The sealant is disposed on the temporary storage base and surrounds the adhesive layer. In addition, other electronic devices and a manufacturing method of the electronic device are also provided.
    Type: Application
    Filed: September 1, 2023
    Publication date: September 26, 2024
    Applicant: AUO Corporation
    Inventors: Cheng-Han Chung, Han-Chung Lai, Yu-Cheng Chang, Po Han Lin, Hsin Hao Chen, Yao-An Mo, Chun-Ming Chao
  • Publication number: 20240322040
    Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.
    Type: Application
    Filed: September 29, 2023
    Publication date: September 26, 2024
    Inventors: Pei Ying Lai, Yi Hsuan Chen, Yen-Fu Chen, Jia-Yun Xu, Cheng-Hao Hou, Da-Yuan Lee, Chi On Chui
  • Publication number: 20240319551
    Abstract: An electronic device is provided. The electronic device includes a substrate and a first conductive line disposed on the substrate and including a first section and a second section electrically connected to the first section. The first section has a first minimum width outside the overlapping region, the second section has a second minimum width outside the overlapping region, and the first minimum width is different from the second minimum width. The electronic device further includes a first conductive layer disposed on the first section and the second section. The first section is electrically connected to the second section through the first conductive layer.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Chih-Hao HSU, Chia-Min YEH, Hsieh-Li CHOU, Cheng-Tso CHEN, Hui-Min HUANG, Li-Wei SUNG, Yu-Ti HUANG
  • Publication number: 20240311638
    Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Nien-Tzu Chou, Yu-Yu Lin, Ching-Fang Lu, Jian-Hao Li, Ting-Hsuan Chen, Cheng-Tai Chen
  • Publication number: 20240304695
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240290630
    Abstract: Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon.
    Type: Application
    Filed: November 28, 2023
    Publication date: August 29, 2024
    Inventors: Pei Ying Lai, Cheng-Chieh Lin, Hsueh-Ju Chen, Tsung-Da Lin, Cheng-Hao Hou, Chi On Chui
  • Publication number: 20240290851
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Patent number: 12074206
    Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen