Patents by Inventor Cheng-Hao Hou
Cheng-Hao Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153823Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20240088204Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing a first conductive material layer over a substrate, patterning the first conductive material layer to form a first conductor plate over the substrate, forming a first high-K dielectric layer over the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, where a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer.Type: ApplicationFiled: March 22, 2023Publication date: March 14, 2024Inventors: Li Chung Yu, Shin-Hung Tsai, Cheng-Hao Hou, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen
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Patent number: 11915979Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.Type: GrantFiled: July 20, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20240021667Abstract: A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.Type: ApplicationFiled: January 10, 2023Publication date: January 18, 2024Inventors: Cheng-Hao Hou, Shin-Hung Tsai, Da-Yuan Lee, Chi On Chui
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Publication number: 20230378294Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Chia-Yuan Chang, Te-Yang Lai, Kuei-Lun Lin, Xiong-Fei Yu, Chi On Chui, Tsung-Da Lin, Cheng-Hao Hou
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Publication number: 20230343818Abstract: A method includes forming a capacitor, which includes forming a first capacitor electrode, forming a first capacitor insulator over the first capacitor electrode, and forming a second capacitor electrode over and contacting the first capacitor insulator. The formation of the first capacitor insulator includes oxidizing a top surface layer of the first capacitor electrode to form a metal oxide layer on the first capacitor electrode, depositing an aluminum oxide layer through a first ALD process having a first plurality of ALD cycles, with the first plurality of ALD cycles having a first ALD cycle number, and depositing a high-k dielectric layer over the aluminum oxide layer. The high-k dielectric layer is deposited through a second ALD process having a second ALD cycle number different from the first ALD cycle number.Type: ApplicationFiled: July 7, 2022Publication date: October 26, 2023Inventors: Shin-Hung Tsai, Cheng-Hao Hou, Te-Yang Lai, Da-Yuan Lee, Chi On Chui
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Patent number: 11756832Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.Type: GrantFiled: January 3, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20230154972Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.Type: ApplicationFiled: January 5, 2022Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-En JENG, Hsiang-Ku SHEN, Cheng-Hao HOU, Chen-Chiu HUANG, Dian-Hau CHEN
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Publication number: 20230139258Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.Type: ApplicationFiled: March 4, 2022Publication date: May 4, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hao Hou, Che-Hao Chang, Da-Yuan Lee, Chi On Chui
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Publication number: 20230063857Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Publication number: 20230069187Abstract: A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Cheng-Hao Hou, Che-Hao Chang, Da-Yuan Lee, Chi On Chui
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Publication number: 20220376077Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.Type: ApplicationFiled: July 28, 2022Publication date: November 24, 2022Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20220367279Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Patent number: 11462626Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.Type: GrantFiled: June 12, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20210399104Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.Type: ApplicationFiled: April 15, 2021Publication date: December 23, 2021Inventors: Chia-Yuan Chang, Te-Yang Lai, Kuei-Lun Lin, Xiong-Fei Yu, Chi On Chui, Tsung-Da Lin, Cheng-Hao Hou
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Patent number: 11107897Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.Type: GrantFiled: July 28, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
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Publication number: 20210126105Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.Type: ApplicationFiled: June 12, 2020Publication date: April 29, 2021Inventors: Chia-Wei Hsu, Pei Ying Lai, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Publication number: 20210098303Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.Type: ApplicationFiled: January 3, 2020Publication date: April 1, 2021Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
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Patent number: 10964543Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.Type: GrantFiled: November 4, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Publication number: 20210028285Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.Type: ApplicationFiled: July 28, 2019Publication date: January 28, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui