Patents by Inventor Cheng-Hsiung Yang

Cheng-Hsiung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Publication number: 20230337372
    Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Songtao Lu, Hsiang Ju Huang, Binbin Zheng, Cheng-Hsiung Yang, Chien-Te Chen
  • Patent number: 11569155
    Abstract: A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: January 31, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chih-Chin Liao, Cheng-Hsiung Yang
  • Publication number: 20220399258
    Abstract: A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Chih-Chin Liao, Cheng-Hsiung Yang
  • Patent number: 11234327
    Abstract: Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 25, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Songtao Lu, Cheng-Hsiung Yang, Yuequan Shi, Ye Bai, Chih-Chin Liao, JinXiang Huang
  • Publication number: 20150262927
    Abstract: A method of manufacturing package carrier is provided. In the method, a holding substrate and a conductive layer are provided. The conductive layer is on the holding substrate. Next, an insulating pattern is formed on the conductive layer. The insulating pattern exposes a portion of the conductive layer. A supporting board is provided. Next, the insulating pattern is detachably connected to the supporting board. After the insulating pattern is detachably connected to the supporting board, the holding substrate is removed, and the conductive layer remains. After removing the holding substrate, the conductive layer is patterned to form a wiring layer.
    Type: Application
    Filed: February 13, 2015
    Publication date: September 17, 2015
    Inventors: CHENG-YU KANG, CHENG-HSIUNG YANG, EN-MIN JOW
  • Patent number: 8858808
    Abstract: A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 14, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventor: Cheng-Hsiung Yang
  • Patent number: 8837808
    Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Chia-Chi Lo, Cheng-Hsiung Yang, Jun-Chung Hsu
  • Publication number: 20140177939
    Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chia-Chi Lo, Cheng-Hsiung Yang, Jun-Chung Hsu
  • Publication number: 20130270216
    Abstract: A method of thin printed circuit board wet process consistency on the same carrier, and more particularly to a printed circuit board in the developing, copper plating, stripping, etching and other wet processes uses the same frame as a carrier from the beginning to the end of the wet process, such that the thin printed circuit board is conducted a continuous and automatic wet process to avoid disassembly, storage and transportation between each process. Moreover, when using the flame, the thin printed circuit board is smooth and flattening in the wet process for avoiding “water effect,” the effective area is not exposed to any mechanical members for preventing scratches, and there are point contacts between the thin printed circuit board and the frame for preventing chemical residue. Accordingly, the present invention can not only enhance the yield of the thin printed circuit board but also shorten the production time.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventor: CHENG-HSIUNG YANG
  • Patent number: 8547548
    Abstract: Disclosed is a final defect inspection system, which including a host device, a microscope, a bar code scanner, a support tool, a signal transceiver and an electromagnetic pen. The bar code scanner scans a bar code on a circuit board provided on the support plate. The host device selects data and a circuit layout diagram from the database corresponding to the bar code. The signal transceiver and the electromagnetic pen are electrically connected to the host device. The electromagnetic pen is used to make a mark on a scrap region of the circuit board where any defect is visually found through the microscope. The signal transceiver receives and transmits the positions of the mark to the host device such that the host device calculates the coordinate of a scrap region based on a relative position between an original point and the positions of the mark.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 1, 2013
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Chia-Chi Lo, Cheng-Hsiung Yang Yang, Jun-Chung Hsu
  • Patent number: 6979886
    Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: December 27, 2005
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jui-Hsiang Hung, Chin-Teng Hsu, Cheng-Hsiung Yang, Chih-Jen Yang
  • Publication number: 20030141577
    Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.
    Type: Application
    Filed: March 29, 2002
    Publication date: July 31, 2003
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jui-Hsiang Hung, Chin-Teng Hsu, Cheng-Hsiung Yang, Chih-Jen Yang