Patents by Inventor CHENG HUNG WANG
CHENG HUNG WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145867Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
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Patent number: 11969236Abstract: A wearable device for measuring blood pressure comprises a housing with through-holes formed thereon, a processing unit disposed in the housing, a display connected to the processing unit, a plurality of sensors connected to the processing unit, the sensors being configured to transmit at least one physiological signal to the processing unit via the through-holes, and a time delay structure connected between one of the through-holes and one of the sensors and configured to lengthen a path distance between the skin surface and the sensor, wherein the processing unit is configured to determine a systolic arterial pressure and a diastolic arterial pressure by the at least one physiological signal and a Moens-Korteweg (MK) function, and to control the display to display the systolic arterial pressure and the diastolic arterial pressure to be read by the user.Type: GrantFiled: May 24, 2019Date of Patent: April 30, 2024Assignee: Accurate Meditech IncInventors: Kuan Jen Wang, Cheng Yan Guo, Ching-Hung Huang
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Publication number: 20240103641Abstract: In one example, a keyboard housing may include a chassis, a plurality of keys exposed through a top surface of the chassis, and an input device assembly connected to the chassis. The input device assembly may include a flexible touch sensing component to receive a touch input and a support structure. The support structure may include a first portion and a second portion foldable onto the first portion. The first portion and the second portion may support the flexible touch sensing component.Type: ApplicationFiled: November 6, 2019Publication date: March 28, 2024Applicant: Hewlett-Packard Development Company, L.P.Inventors: Cheng-Han Tsai, Midas Wu, Wen-Hung Wang
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Patent number: 11935795Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: July 28, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 11894381Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.Type: GrantFiled: October 28, 2019Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Jung Chen, Tsung-Lin Lee, Chung-Ming Lin, Wen-Chih Chiang, Cheng-Hung Wang
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Publication number: 20230282552Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Inventors: Kuan-Jung CHEN, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
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Patent number: 11688666Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.Type: GrantFiled: June 1, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
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Patent number: 11508628Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: September 15, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Publication number: 20220367523Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
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Publication number: 20220367276Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Cheng-Hung WANG, Tsung-Lin LEE, Wen-Chih CHIANG, Kuan-Jung CHEN
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Publication number: 20220084887Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Cheng-Hung WANG, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Publication number: 20210287963Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
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Patent number: 11031320Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.Type: GrantFiled: November 6, 2019Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
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Publication number: 20200176359Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.Type: ApplicationFiled: November 6, 2019Publication date: June 4, 2020Inventors: Kuan-Jung Chen, Cheng-Hung Wang, Tsung-Lin Lee, Shiuan-Jeng Lin, Chun-Ming Lin, Wen-Chih Chiang
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Publication number: 20200161335Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.Type: ApplicationFiled: October 28, 2019Publication date: May 21, 2020Inventors: Kuan-Jung CHEN, Tsung-Lin LEE, Chung-Ming LIN, Wen-Chih CHIANG, Cheng-Hung WANG
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Patent number: 10395997Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.Type: GrantFiled: January 18, 2017Date of Patent: August 27, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Cheng Tsao, Cheng-Hung Wang, Chun-Chieh Lin, Hsiu-Hsiung Yang, Yu-Pin Tsai
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Publication number: 20170125310Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Cheng TSAO, Cheng-Hung WANG, Chun-Chieh LIN, Hsiu-Hsiung YANG, Yu-Pin TSAI
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Patent number: D1021220Type: GrantFiled: July 15, 2021Date of Patent: April 2, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Cheng-Ang Chang, Guo-Hao Huang, Chun-Yi Sun, Chih-Hung Ju, Pin-Tsung Wang