Patents by Inventor Cheng Hung Yeh
Cheng Hung Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694973Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: GrantFiled: June 23, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Publication number: 20230205967Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
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Patent number: 11586797Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.Type: GrantFiled: February 19, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
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Publication number: 20220320018Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
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Publication number: 20220246509Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
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Patent number: 11387177Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: GrantFiled: June 17, 2019Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Her Chien, Po-Hsiang Huang, Cheng-Hung Yeh, Tai-Yu Wang, Ming-Ke Tsai, Yao-Hsien Tsai, Kai-Yun Lin, Chin-Yuan Huang, Kai-Ming Liu, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11367695Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.Type: GrantFiled: June 12, 2019Date of Patent: June 21, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen, Aftab Alam Khan, Keh-Jeng Chang, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20210320072Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Patent number: 11088084Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: GrantFiled: April 30, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Publication number: 20210173998Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
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Patent number: 10949597Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.Type: GrantFiled: July 2, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
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Publication number: 20200395281Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
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Publication number: 20200258846Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Chin-Chou LIU, Cheng-Hung YEH, Fong-Yuan CHANG, Po-Hsiang HUANG, Yi-Kan CHENG, Ka Fai CHANG
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Patent number: 10665550Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: GrantFiled: July 24, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Publication number: 20200043873Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.Type: ApplicationFiled: June 12, 2019Publication date: February 6, 2020Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
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Publication number: 20200019668Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.Type: ApplicationFiled: July 2, 2019Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan CHANG, Chin-Chou Liu, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
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Publication number: 20200020644Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.Type: ApplicationFiled: July 24, 2018Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
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Publication number: 20180132728Abstract: An apparatus for holding an imaging subject, such as a whole animal, within a photoacoustic computed tomography system with dry acoustic coupling is disclosed. The apparatus includes a dry acoustic coupler with a tubular elastic membrane made of an optically and acoustically transmissive material. The tubular elastic membrane defines a lumen and at least one lumen opening proximate to a membrane end. In use, the lumen of the tubular elastic membrane is positioned within a coupling fluid contained within a tank of the photoacoustic computed tomography system. The apparatus enables contact-free acoustic coupling of the imaging subject with the coupling fluid during PA imaging. The tank may be optionally pressurized to enhance stabilization of the imaging subject within the coupling fluid.Type: ApplicationFiled: November 2, 2017Publication date: May 17, 2018Inventors: Lihong Wang, Cheng-hung Yeh, Lei Li
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Patent number: 9666490Abstract: Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The first device layer comprises one or more first inverter structures including a first input terminal and a first output terminal. A second device layer is formed on the first device layer. The second device layer comprises one or more second inverter structures including a second input terminal and a second output terminal. One or more inter-layer connection structures are formed. The one or more inter-layer connection structures are disposed to electrically connect the first input terminal to the second output terminal and electrically connect the first output terminal to the second input terminal.Type: GrantFiled: June 6, 2016Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
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Publication number: 20160284603Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: I-Fan Lin, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN