Abstract: An electronic device is provided. The electronic device includes a substrate structure, a control unit, a first circuit structure, and an electronic unit. The substrate structure has a conductive via pattern and a dummy via pattern. The control unit is electrically connected to the conductive via pattern. The first circuit structure is electrically connected to the conductive via pattern. The electronic unit is electrically connected to the control unit through the first circuit structure. The dummy via pattern is electrically insulated from the first circuit structure.

Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.

Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.

Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.

Abstract: A circuit protection apparatus (100) is used to protect an LED drive circuit (200), and the circuit protection apparatus (100) includes a first switch unit (1) and a snubber circuit (3). The first switch unit (1) provides an electrical connection between an input terminal (100A) and the LED drive circuit (200) according to the normality of an input current (Iin) flowing through the input terminal (100A). The snubber circuit (3) provides a first delay time period (Td1) according to an input power (Vin). The snubber circuit (3) provides a start signal (Ss) to the LED drive circuit (200) according to the end of the first delay time period (Td1), and controls a first ground point (G1) of the snubber circuit (3) to be coupled to a second ground point (G2) of the LED drive circuit (200).

Abstract: A controlling module controls illuminant state of an illuminant module according to a controlling signal sent form a wireless controller. The controlling module is electrically connected to the illuminant module and includes a microprocessor, a wireless receiver, a regulator, and a driving unit. The wireless receiver is electrically connected to the microprocessor and receives the controlling signal sent form the wireless controller. The regulator is electrically connected to the microprocessor. The driving unit is electrically connected to the microprocessor and the illuminant module.

Abstract: A smart light emitting diode driving apparatus includes a micro processing unit and a light emitting diode driving circuit. An optical detection equipment is configured to send an optics characteristic signal to a computer after an optics characteristic of a light emitting diode is detected by the optical detection equipment. The computer is configured to send a control signal to the micro processing unit after the optics characteristic signal is processed by the computer. The micro processing unit is configured to record the control signal. The micro processing unit is configured to control the light emitting diode driving circuit in accordance with the control signal. The light emitting diode driving circuit is configured to output a driving current to drive the light emitting diode.