Patents by Inventor Cheng-Kuo Lin
Cheng-Kuo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170203959Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.Type: ApplicationFiled: March 30, 2017Publication date: July 20, 2017Inventors: PEI-CHUN LIAO, PO-WEI TING, CHIH-FENG CHIANG, YU-KAI WU, YU-FAN CHANG, RE-CHING LIN, SHU-HSIAO TSAI, CHENG-KUO LIN
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Publication number: 20170170233Abstract: An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Shu-Hsiao TSAI, Re Ching LIN, Pei-Chun LIAO, Cheng-Kuo LIN, Yung-Chung CHIN
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Publication number: 20170162518Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.Type: ApplicationFiled: May 5, 2016Publication date: June 8, 2017Inventors: PEI-CHUN LIAO, PO-WEI TING, CHIH-FENG CHIANG, YU-KAI WU, YU-FAN CHANG, RE-CHING LIN, SHU-HSIAO TSAI, CHENG-KUO LIN
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Patent number: 9673186Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: GrantFiled: March 31, 2015Date of Patent: June 6, 2017Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
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Patent number: 9653516Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wType: GrantFiled: December 30, 2014Date of Patent: May 16, 2017Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin
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Publication number: 20170134000Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wType: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventors: Shu-Hsiao TSAI, Re Ching LIN, Pei-Chun LIAO, Cheng-Kuo LIN, Yung-Chung CHIN
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Publication number: 20170110400Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.Type: ApplicationFiled: March 10, 2016Publication date: April 20, 2017Inventors: Shu-Hsiao TSAI, Rong-Hao SYU, Yi-Ling LIU, Cheng-Kuo LIN
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Publication number: 20170084592Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Shinichiro TAKATANI, Hsien-Fu Hsiao, Cheng-Kuo LIN, Chang-Hwang HUA
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Publication number: 20170077899Abstract: A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.Type: ApplicationFiled: March 15, 2016Publication date: March 16, 2017Inventors: Cheng-Kuo Lin, Shu-Hsiao Tsai, Rong-Hao Syu, Yi-Ling Liu, Re-Ching Lin, Pei-Chun Liao
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Publication number: 20160322482Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two recesses respectively on two opposite sides of the “H” shape, and the emitter has two elongated emitter electrodes formed on the “H” shaped emitter. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, and each of the base electrodes has a base via hole at or near the center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.Type: ApplicationFiled: July 7, 2016Publication date: November 3, 2016Inventors: Jui-Pin CHIU, Shu-Hsiao TSAI, Rong-Hao SYU, Cheng-Kuo LIN
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Publication number: 20160247797Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.Type: ApplicationFiled: April 29, 2016Publication date: August 25, 2016Inventors: Shu-Hsiao TSAI, Hsiu-Chen CHANG, Shinichiro TAKATANI, Cheng-Kuo LIN
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Publication number: 20160190206Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wType: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shu-Hsiao TSAI, Re Ching LIN, Pei-Chun LIAO, Cheng-Kuo LIN, Yung-Chung CHIN
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Patent number: 9356127Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.Type: GrantFiled: June 7, 2013Date of Patent: May 31, 2016Assignee: WIN SEMICONDUCTORS CORP.Inventors: Shu-Hsiao Tsai, Hsiu-Chen Chang, Shinichiro Takatani, Cheng-Kuo Lin
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Publication number: 20160020307Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.Type: ApplicationFiled: April 21, 2015Publication date: January 21, 2016Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
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Publication number: 20150206870Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA
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Patent number: 9087923Abstract: A monolithic compound semiconductor structure is disclosed. The monolithic compound semiconductor structure comprises a substrate, an n-type FET epitaxial structure, an n-type etching-stop layer, a p-type insertion layer, and an npn HBT epitaxial structure, and it can be used to form an FET, an HBT, or a thyristor.Type: GrantFiled: October 26, 2012Date of Patent: July 21, 2015Assignee: WIN SMICONDUTOR CORP.Inventors: Cheng-Kuo Lin, Szu-Ju Li, Rong-Hao Syu, Shu-Hsiao Tsai
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Patent number: 9019028Abstract: An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.Type: GrantFiled: October 26, 2012Date of Patent: April 28, 2015Assignee: WIN Semiconductors Corp.Inventors: Cheng-Kuo Lin, Szu-Ju Li, Rong-Hao Syu, Shu-Hsiao Tsai
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Publication number: 20140312390Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.Type: ApplicationFiled: June 7, 2013Publication date: October 23, 2014Inventors: Shu-Hsiao TSAI, Hsiu-Chen CHANG, Shinichiro TAKATANI, Cheng-Kuo LIN
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Publication number: 20140231876Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Applicant: WIN Semiconductors Corp.Inventors: Shu-Hsiao TSAI, Cheng-Kuo LIN, Bing-Shan HONG, Shinichiro Takatani
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Publication number: 20140209926Abstract: A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: WIN SEMICONDUCTORS CORP.Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Cheng-Kuo LIN, Chang-Hwang HUA