Patents by Inventor Cheng-Lung Wu

Cheng-Lung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153806
    Abstract: An apparatus for automated wafer carrier handling includes a base plate and an active expansion component movably coupled to the base plate. The active expansion component is configured to change from a contracted form to an expanded form so as to be engaged with a top flange mounted on a wafer carrier.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
  • Patent number: 11975958
    Abstract: An automatic fluid replacement device is adapted to be mounted on an opening of a storage barrel. The automatic fluid replacement device includes a robotic arm, at least one fluid convey joint and a controller. The robotic arm has a gripper. The fluid convey joint includes a convey pipe, a sleeve and a sealing bag. The convey pipe is configured to deliver a fluid. The sleeve is sleeved on the convey pipe. The gripper clamps the sleeve. The sealing bag is sleeved on the sleeve. The controller is configured for automatically controlling the robotic arm to move the fluid convey joint into the opening and controlling the sealing bag to be inflated to seal the opening.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: May 7, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Han Tsai, Wei-Lung Pan, Chih-Ta Wu, I-hsin Lin
  • Patent number: 11972971
    Abstract: A wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. This enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. A controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. This enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Chen, Yi-Fam Shiu, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11951569
    Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11954841
    Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Lieh Chen, Cheng-Kang Hu, Cheng-Lung Wu, Jiun-Rong Pai
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11923225
    Abstract: A method includes initiating a gas flow of a first gas parallel to a wall of an interface module to create an air curtain across an opening defined in the wall. The method includes moving an interface door to reveal the opening, wherein the air curtain restrains a second gas within the interface module from passing through the opening. The method includes transferring a semiconductor wafer through the opening and moving the interface door to cover the opening. The method includes halting the gas flow of the first gas after moving the interface door to cover the opening.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Fam Shiu, Cheng-Lung Wu, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
  • Publication number: 20240067512
    Abstract: An automatic fluid replacement device is adapted to be mounted on an opening of a storage barrel. The automatic fluid replacement device includes a robotic arm, at least one fluid convey joint and a controller. The robotic arm has a gripper. The fluid convey joint includes a convey pipe, a sleeve and a sealing bag. The convey pipe is configured to deliver a fluid. The sleeve is sleeved on the convey pipe. The gripper clamps the sleeve. The sealing bag is sleeved on the sleeve. The controller is configured for automatically controlling the robotic arm to move the fluid convey joint into the opening and controlling the sealing bag to be inflated to seal the opening.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 29, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Han TSAI, Wei-Lung PAN, Chih-Ta WU, I-hsin LIN
  • Patent number: 11915958
    Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
  • Patent number: 11915957
    Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Yi-Fam Shiu, Yu-Chen Chen, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11915954
    Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Zheng-Lin He, Yang-Ann Chu, Jiun-Rong Pai, Hsuan Lee
  • Publication number: 20240001409
    Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 4, 2024
    Inventors: Kuang-Wei Cheng, Cheng-Lung Wu, Chyi-Tsong Ni
  • Publication number: 20230386877
    Abstract: A system comprises a front opening universal pod (FOUP) configured to hold one or more semiconductor wafers and a load dock having a stage and a receiving portion extending above the stage. The FOUP is positioned on the stage. A fan filter unit (FFU) positioned above the load dock. An air flow optimizer device is disposed on the receiving portion and under the FFU. The air flow optimizer device has an inlet opening and an outlet opening and a channel extends between the inlet opening and the outlet opening.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Yi-Fam Shiu, Cheng-Lung Wu, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
  • Publication number: 20230369082
    Abstract: The present disclosure provides an embodiment of a semiconductor fabrication system. The semiconductor fabrication system includes an equipment front end module with a load port to transfer semiconductor wafers to the equipment front end module from a wafer carrier; and a wafer humidity control device embedded in the equipment front end module and configured to generate an air curtain to protect the semiconductor wafers. The wafer humidity control device further includes a gas entry layer with a gas inlet to receive a gas; a uniform layer integrated with the gas entry layer and designed to redistribute the gas; and a diversion structure having multiple pieces assembled together to hold the uniform layer and integrated with the gas entry layer.
    Type: Application
    Filed: August 10, 2022
    Publication date: November 16, 2023
    Inventors: Cheng-Lung Wu, Yi-Fam Shiu, Yang-Ann Chu, Hsu-Shui Liu
  • Publication number: 20230335424
    Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.
    Type: Application
    Filed: May 15, 2023
    Publication date: October 19, 2023
    Inventors: Chih-Hung HUANG, Cheng-Lung WU, Yang-Ann CHU, Hsuan LEE, Jiun-Rong PAI
  • Publication number: 20230302589
    Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener from the pod, and the fastener head is received within the lower sleeve.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 28, 2023
    Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11752582
    Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener from the pod, and the fastener head is received within the lower sleeve.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • Publication number: 20230268210
    Abstract: A tray of an automated handling system for transporting semiconductor devices includes: a receiving region that is configured to receive a boat, the boat carrying one or more semiconductor devices thereon; and a clamping mechanism that selectively clamps the boat, residing in the receiving region, to the tray. Suitably, the clamping mechanism is automatically disengaged when the tray is positioned in a designated location and automatically engaged when the tray is not positioned in the designated location, such that, when engaged, the clamping mechanism holds the boat, residing in the boat receiving region, securely within the tray, and when disengaged, the clamping mechanism releases the boat residing in the boat receiving region.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Inventors: CHUN-YU LIN, Chih-Hung Huang, Yu-Chen Chen, Cheng-Lung Wu, Jiun-Rong Pai
  • Patent number: 11735455
    Abstract: A system comprises a front opening universal pod (FOUP) configured to hold one or more semiconductor wafers and a load dock having a stage and a receiving portion extending above the stage. The FOUP is positioned on the stage. A fan filter unit (FFU) positioned above the load dock. An air flow optimizer device is disposed on the receiving portion and under the FFU. The air flow optimizer device has an inlet opening and an outlet opening and a channel extends between the inlet opening and the outlet opening.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Fam Shiu, Cheng-Lung Wu, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai