Patents by Inventor CHENG-MING CHUANG

CHENG-MING CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11955535
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11935825
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
  • Publication number: 20240087949
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
  • Patent number: 11929321
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang
  • Patent number: 11916133
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20190321691
    Abstract: The present invention provides a composite ball with high wear resistance and waterproofness, which comprises a bladder layer, an attached sheet layer, and a protective layer, the bladder layer comprises a solid ball filled with an elastic material, the attached sheet layer comprises an upper attached sheet layer and a lower attached sheet layer, and the attached external surfaces of the upper attached sheet layer and the lower attached sheet layer are also covered by the protective layer which is molded by injecting the elastic material. As the present invention adopts the injection molding method to form the protective layer on the surface of the attached sheet layer, the present invention has special waterproof and wear-resisting properties in comparison with conventional balls.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventor: Cheng-Ming CHUANG
  • Patent number: 9950217
    Abstract: The utility model discloses a multilayer composite high-elastic environmentally-friendly ball structure which comprises a base layer, a first coating layer, a second coating layer, a third coating layer and a fourth coating layer, wherein both the base layer and the first coating layer are formed by splicing a number of pieces into a hollow spherical structure, and a contact surface of two adjacent spliced pieces is a stepped surface in a “Z” shape or a concave-convex fitting surface in a “U” shape. The utility model have the advantages of simple manufacturing process, novel design, high stability, high reliability, high elasticity and long service life.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 24, 2018
    Inventor: Cheng-Ming Chuang
  • Publication number: 20170326413
    Abstract: An elastic solid ball structure of the present invention includes at least a thermoplastic polyurethane foam sphere center and a first adhesive layer, a first spherical lamina, a second adhesive layer, and a second spherical lamina sequentially disposed on the external surface of the thermoplastic polyurethane foam sphere center. The overall diameter of the elastic solid ball structure is 8 cm-26 cm. In addition, at least one protruding portion or at least one indentation portion is formed on the external surface of the thermoplastic polyurethane foam sphere center, thereby forming an irregular circular surface thereon. The described structural design provides the elastic solid ball structure of the present invention with advantages including good elasticity, a long serviceable life, permanently dispensing with the need to inflate, and eliminating having to re-inflate the ball structure.
    Type: Application
    Filed: May 16, 2016
    Publication date: November 16, 2017
    Inventor: CHENG-MING CHUANG
  • Publication number: 20170087418
    Abstract: An elastic solid ball structure disclosed in the present invention consists of at least a thermoplastic polyurethane foam sphere center formed from thermoplastic polyurethane foam; and a first adhesive layer, a first spherical lamina, a second adhesive layer, and a second spherical lamina sequentially disposed on the external surface of the thermoplastic polyurethane foam sphere center; wherein the overall diameter of the elastic solid ball structure is 8 cm˜26 cm. Moreover, at least one surface of the second spherical lamina can be additionally provided with printed layers. Accordingly, the aforementioned structural design provides the present invention with advantages including design originality, good elasticity, a long serviceable life, permanently dispensing with the need to inflate, and eliminating the need to re-inflate, as well as saving on the need to purchase an inflating device.
    Type: Application
    Filed: March 21, 2016
    Publication date: March 30, 2017
    Inventor: CHENG-MING CHUANG