Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.

Abstract: An electronic device including a circuit structure, a bonding element and an electronic unit is disclosed. The circuit structure includes a conductive pad, and the conductive pad has an accommodating recess. At least a portion of the bonding element is disposed in the accommodating recess. The electronic unit is electrically connected to the conductive pad through the bonding element. The accommodating recess has a bottom surface and an opening opposite to the bottom surface, and a width of the bottom surface is greater than a width of the opening.

Abstract: The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.

Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: An electronic apparatus and a secure firmware update method thereof are provided. The electronic apparatus includes a first integrated circuit chip, a first non-volatile memory chip, a second integrated circuit chip and a second non-volatile memory chip. The first integrated circuit chip includes a secure firmware update console, and the first non-volatile memory chip includes a spare data storage space. The first non-volatile memory chip and the second non-volatile memory chip store a first firmware code of the first integrated circuit chip and a second firmware code of the second integrated circuit chip, respectively. Firmware code update data are transferred to and stored in the spare data storage space. The secure firmware update console performs a firmware update procedure by writing the firmware code update data into the second non-volatile memory chip to overwrite the second firmware code after passing a verification procedure on the firmware code update data.

Abstract: A method of removing hydrogen peroxide from sulfuric acid includes the following steps: First step of pouring the sulfuric acid having 0.1 wt % to 10 wt % of hydrogen peroxide into a vessel. Second step of adding a catalyst containing copper and a copper compound to the vessel to undergo a reaction with the sulfuric acid to remove the hydrogen peroxide from the sulfuric acid, to generate heat, and to generate metal ions in the sulfuric acid. Third step of activating a cooling device to cool the vessel to a predetermined temperature range. Fourth step of adding hydrogen sulfide to the vessel to undergo a reaction with the metal ions to generate metallic sulfide and metal free sulfuric acid. Fifth step of purifying the metallic sulfide and the metal free sulfuric acid to obtain purified metallic sulfide and purified sulfuric acid as products.

Abstract: An electronic apparatus and a secure firmware update method thereof are provided. The electronic apparatus includes a first integrated circuit chip, a first non-volatile memory chip, a second integrated circuit chip and a second non-volatile memory chip. The first integrated circuit chip includes a secure firmware update console, and the first non-volatile memory chip includes a spare data storage space. The first non-volatile memory chip and the second non-volatile memory chip store a first firmware code of the first integrated circuit chip and a second firmware code of the second integrated circuit chip, respectively. Firmware code update data are transferred to and stored in the spare data storage space. The secure firmware update console performs a firmware update procedure by writing the firmware code update data into the second non-volatile memory chip to overwrite the second firmware code after passing a verification procedure on the firmware code update data.

Abstract: A method of removing hydrogen peroxide from sulfuric acid includes pouring sulfuric acid (H2SO4) having 0.1% to 10% of hydrogen peroxide (H2O2) into a vessel; adding a catalyst containing metal or metal compound to the vessel to undergo a reaction with the sulfuric acid (H2SO4) to remove hydrogen peroxide (H2O2) from the sulfuric acid (H2SO4), to generate heat, and to generate metal ions in the sulfuric acid (H2SO4); activating a cooling device to cool the vessel to a predetermined temperature range; adding sulfur (S2?) to the vessel to undergo a reaction with the metal ions to generate metallic sulfide; and purifying the metal free sulfuric acid (H2SO4) to obtain the metallic sulfide and highly purified, diluted sulfuric acid (H2SO4) as products.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

Abstract: A cutting device and a cutting method of a liquid crystal panel are provided. The liquid crystal panel includes a first substrate and a second substrate assembled together. The cutting device of the liquid crystal panel includes a first cutting portion for cutting the first substrate and a second cutting portion for cutting the second substrate. The second cutting portion includes a support portion. The support portion is used to support the first substrate when the first cutting portion cuts the first substrate and the second cutting portion does not cut the second substrate yet. The present invention assures the cutting quality, improves the cutting efficiency and reduces the cutting cost.