Abstract: An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulator electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.

Abstract: A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission channel into different channel modes according to received configurations; simulating a plurality of pulse signals into the analog transmission channel according to the received configurations, and recording an impulse response of each of the channel modes; simulating differential signal transmissions of the differential signals according to the received configurations, and analyzing the differential signal transmissions into different signal modes corresponding to the different channel modes; transforming each signal mode and the impulse response of a corresponding channel mode to respectively generate a first value and a second value by utilizing Fast Fourier Transform Algorithm; multiplying the first value by the second value to generate a third va

Abstract: A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.

Abstract: An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, a voltage regulator electronically connected to the first slot and the second slot, and a serial presence detect (SPD) unit connected to the voltage regulator. The first memory and the second memory alternatively mounted on the motherboard, the SPD detects which type of memory is mounted on the motherboard, and the voltage regulator outputs voltages suitable for the type of the memory mounted on the motherboard according to a detection result of the SPD.

Abstract: A motherboard includes a chipset, a first connector pad suitable for receiving a first type of PCI connector, a second connector pad suitable for receiving a second type of PCI connector, a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of areas for mounting switches. One end of each first transmission line is connected to the chipset, another end of each first transmission line is connected to an end of a corresponding area, one end of each second transmission line is connected to another end of the corresponding area, another end of each second transmission line is connected to the second connector pad, the first connector pad is connected to the plurality of first transmission lines, and the switches are selectively mounted on the plurality of areas.

Abstract: A printed circuit board includes a first signal layer, a second signal layer, a plurality of transmission lines respectively including first segments laid in parallel on the first signal layer and second segments laid in parallel on the second signal layer, and a plurality of vias, each via connecting the first segment with the second segment of a corresponding transmission line. One of the plurality of transmission lines has the first segment positioned in the middle of an array defined by the first segments of the plurality of transmission lines, and a second segment positioned in an outmost position of an array defined by the second segments of the plurality of transmission lines. The printed circuit board reduces the possibility of false action of electronic components coupled to transmission lines, which is caused by the crosstalk between transmission lines.

Abstract: A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.

Abstract: A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission channel into different channel modes according to received configurations; simulating a plurality of pulse signals into the analog transmission channel according to the received configurations, and recording an impulse response of each of the channel modes; simulating differential signal transmissions of the differential signals according to the received configurations, and analyzing the differential signal transmissions into different signal modes corresponding to the different channel modes; transforming each signal mode and the impulse response of a corresponding channel mode to respectively generate a first value and a second value by utilizing Fast Fourier Transform Algorithm; multiplying the first value by the second value to generate a third va

Abstract: A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device (9); simulating the differential signal paths based on the design file; dividing simulated differential signal paths into a plurality of segments by impedance division positions that show impedance discontinuity; predefining an acceptable length difference limit for each divided segment, and calculating an real length difference for each divided segment; comparing the real length difference with the acceptable length difference limit correspondingly to generate a plurality of analyzed results corresponding to the plurality of divided segments; selecting one or more compared segments to check analyzed results of selected segments; and locating the selected segments in the simulated differential signal paths, and generating analyzed information comprising analyzed results of the selected segments. A related system is also disclosed.

Abstract: A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module (301) for generating an N-bit binary sequence consisting of “1” and “0” according to signal source parameters; a application module (302) for applying the N-bit binary sequence to generate the various simulation conditions according to control parameters; a noise generating module (303) for generating N influence values of Gauss noises with N standard deviations to N signal bit-widths; and an addition module (304) for adding the Gauss noises to corresponding digital waveform positions of the generated simulation conditions. A related method is also disclosed.

Abstract: An exemplary signal transmitting circuit includes a driving circuit, a main transmission line, a resistor, a node and a plurality of receiving circuits. The driving circuit is coupled to the node via the resistor and the main transmission line. Each of the receiving circuits is coupled to the node via an offshoot transmission line. The lengths of the offshoot transmission lines are generally equal to each other. It is of advantage that the signal transmitting circuit reduces signal reflections and maintains signal integrity.

Abstract: A system and method for generating various jitter analysis diagrams and customized jitter analysis reports. The method includes the steps of: (a) obtaining a signal file; (b) determining a type of the signal file; (c) loading customized jitter analysis parameters; (d) generating a graphic function according to the customized jitter analysis parameters; (e) obtaining serial signals from the signal file; (f) separating transient signals and non-transient signals from the serial signals; (g) rebuilding an ideal clock based on the serial signals by means of performing a minimum deviation algorithm (MDA); (h) calculating and analyzing jitters of the serial signals according to the ideal clock by means of performing the MDA; (i) generating a jitter analysis diagram according to the graphic function; and (j) generating a jitter analysis report according the jitter analysis results.

Abstract: The present invention provides a system and a method for analyzing jitter of various signals including measurement signals and simulation signals. The method includes the steps of: (a) obtaining a signal file; (b) identifying a type of the signal file; (c) defining a jitter analysis mode from a phase jitter mode, a periodic jitter mode and a cycle jitter mode; (d) obtaining an n-bit differential signal from the signal file; (e) rebuilding an ideal clock based on the differential signal by means of performing a Minimum Deviation Algorithm (MDA); (f) calculating and analyzing jitter of the differential signal according to the ideal clock by means of performing the MDA; and (g) generating and outputting a jitter analysis wave and jitter analysis results according to the defined jitter analysis mode.