Patents by Inventor Cheng-Ta Ko

Cheng-Ta Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190239362
    Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Cheng-Ta KO, John Hon-Shing LAU, Yu-Hua CHEN, Tzyy-Jang TSENG
  • Patent number: 10324370
    Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 18, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Shih-Lian Cheng, Yu-Hua Chen, Cheng-Ta Ko, Jui-Jung Chien, Wei-Tse Ho
  • Publication number: 20190139907
    Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Pu-Ju LIN, Cheng-Ta KO, Yu-Hua CHEN, Tzyy-Jang TSENG, Ra-Min TAIN
  • Patent number: 10121673
    Abstract: In an embodiment, a miniaturize particulate matter detector includes a filter having a plurality of holes, and a concentration detector correspondingly disposed under the filter. The concentration detector has a detect area used for detecting a concentration of at least one miniaturize particulate matter. A manufacturing method of the filter is also provided.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 6, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Chiang, Cheng-Ta Ko, I-Hsing Lin
  • Patent number: 10083901
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: September 25, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Cheng-Ta Ko
  • Publication number: 20180122733
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Application
    Filed: December 25, 2017
    Publication date: May 3, 2018
    Inventors: Yu-Hua CHEN, Cheng-Ta KO
  • Patent number: 9931813
    Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Kuan-Neng Chen, Wei-Chung Lo, Cheng-Ta Ko
  • Publication number: 20180070452
    Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Shih-Lian Cheng, Yu-Hua Chen, Cheng-Ta Ko, Jui-Jung Chien, Wei-Tse Ho
  • Patent number: 9887153
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 6, 2018
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yu-Hua Chen, Cheng-Ta Ko
  • Publication number: 20180005931
    Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
    Type: Application
    Filed: September 6, 2016
    Publication date: January 4, 2018
    Inventors: Yu-Hua CHEN, Cheng-Ta KO
  • Publication number: 20170374748
    Abstract: A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Wang-Hsiang TSAI, Cheng-Ta KO
  • Publication number: 20170153214
    Abstract: An optical sensing module, adapted to sense a characteristic of an object by a sensing beam, comprises a carrying substrate, a transparent cover having a reflective surface thereon, a side wall, an optical grating, and an optical sensor. The reflective surface has a light-transmissive opening that exposes a part of the transparent cover. The side wall is disposed around the carrying substrate and is located between the carrying substrate and the transparent cover. The optical grating is disposed on the carrying substrate and a position of the optical grating corresponds to the light-transmissive opening. The optical sensor is disposed on the carrying substrate and is located at a side of the optical grating, wherein the carrying substrate, the side wall and the transparent cover form a vacuum chamber. The optical grating and the optical sensor are disposed in the vacuum chamber.
    Type: Application
    Filed: November 26, 2015
    Publication date: June 1, 2017
    Inventors: Chin-Hung Wang, Cheng-Ta Ko, Sheng-Shu Yang
  • Publication number: 20170052102
    Abstract: In an embodiment, a miniaturize particulate matter detector includes a filter having a plurality of holes, and a concentration detector correspondingly disposed under the filter. The concentration detector has a detect area used for detecting a concentration of at least one miniaturize particulate matter. A manufacturing method of the filter is also provided.
    Type: Application
    Filed: November 30, 2015
    Publication date: February 23, 2017
    Inventors: Chia-Wen Chiang, Cheng-Ta Ko, I-Hsing Lin
  • Publication number: 20170052103
    Abstract: A miniaturized particulate matter detector that includes a filter and a concentration detector is provided. The filter has a plurality of holes, and the concentration detector is correspondingly disposed under the filter. The concentration detector has a detected area used to detect a concentration of at least one miniaturized particulate matter. A manufacturing method of the filter is also provided.
    Type: Application
    Filed: August 24, 2016
    Publication date: February 23, 2017
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Wen Chiang, Cheng-Ta Ko, I-Hsing Lin, Hsiang-Hung Chang, Wen-Chih Chen
  • Patent number: 9373564
    Abstract: A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 21, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Wei Shen, Kuan-Neng Chen, Cheng-Ta Ko
  • Publication number: 20160043018
    Abstract: A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 11, 2016
    Inventors: Wen-Wei Shen, Kuan-Neng Chen, Cheng-Ta Ko
  • Publication number: 20160043239
    Abstract: Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 11, 2016
    Inventors: Hsiang-Hung Chang, Wen-Chih Chen, Chia-Wei Jui, Zhi-Cheng Hsiao, Cheng-Ta Ko, Rong-Shen Lee, Sheng-Shu Yang
  • Patent number: 9130080
    Abstract: An encapsulation of backside illumination photosensitive device including a circuit sub-mount, a backside illumination photosensitive device, a plurality of conductive terminals, and a heat dissipation structure is provided. The backside illumination photosensitive device includes an interconnection layer and a photosensitive device array, wherein the interconnection layer is located on the circuit sub-mount, and between the photosensitive device array and the circuit sub-mount. The conductive terminals are located between the interconnection layer and the circuit sub-mount to electrically connect the interconnection layer and the circuit sub-mount. The heat dissipation structure is located under the interconnection layer, and the heat dissipation structure and the photosensitive device array are respectively located at two opposite sides of the interconnection layer.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 8, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Zhi-Cheng Hsiao, Ming-Ji Dai, Cheng-Ta Ko
  • Publication number: 20150097259
    Abstract: Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Hsiang-Hung CHANG, Wen-Chih CHEN, Chia-Wei JUI, Zhi-Cheng HSIAO, Cheng-Ta KO, Rong-Shen LEE, Sheng-Shu YANG
  • Publication number: 20140291790
    Abstract: An encapsulation of backside illumination photosensitive device including a circuit sub-mount, a backside illumination photosensitive device, a plurality of conductive terminals, and a heat dissipation structure is provided. The backside illumination photosensitive device includes an interconnection layer and a photosensitive device array, wherein the interconnection layer is located on the circuit sub-mount, and between the photosensitive device array and the circuit sub-mount. The conductive terminals are located between the interconnection layer and the circuit sub-mount to electrically connect the interconnection layer and the circuit sub-mount. The heat dissipation structure is located under the interconnection layer, and the heat dissipation structure and the photosensitive device array are respectively located at two opposite sides of the interconnection layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: October 2, 2014
    Inventors: Zhi-Cheng Hsiao, Ming-Ji Dai, Cheng-Ta Ko