Patents by Inventor Cheng-Ting Chen
Cheng-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11342321Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.Type: GrantFiled: January 12, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
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Publication number: 20220071333Abstract: The present invention provides a safety helmet inner lining adjustable for suitable wearing, consisting of: a covering body, which has an inner side surface that contacts a user's head and an outer side surface relative to the inner side surface; at least one interlayer pocket, which is disposed on the outer side surface of the covering body; and at least one cushiony pad, which is suitable for placement inside the interlayer pocket. A user is able to place the cushiony pads of suitable thickness into the interlayer pockets at preset positions according to the user's to head shape and dimensions. The inner lining is then put onto the head and a safety helmet put on top. The cushiony pads enable correcting the interspace between the user's head and the safety helmet, thereby allowing suitable and perfect fitting of the safety helmet that ensures safety of the wearer.Type: ApplicationFiled: September 30, 2020Publication date: March 10, 2022Inventor: Cheng-Ting CHEN
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Patent number: 11158605Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.Type: GrantFiled: October 23, 2017Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
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Publication number: 20210263243Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
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Publication number: 20210233829Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11002927Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.Type: GrantFiled: February 21, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
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Patent number: 10978370Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: GrantFiled: September 13, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 10903090Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.Type: GrantFiled: May 16, 2019Date of Patent: January 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ting Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Wei-Yu Chen, Chia-Lun Chang, Chia-Shen Cheng, Cheng-Shiuan Wong
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Patent number: 10879203Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.Type: GrantFiled: September 18, 2017Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20200365420Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ting Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hao-Jan Pei, Wei-Yu Chen, Chia-Lun Chang, Chia-Shen Cheng, Cheng-Shiuan Wong
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Patent number: 10784221Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.Type: GrantFiled: December 6, 2011Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Jen Lin, Chung-Shi Liu, Ming-Da Cheng, Chung-Cheng Lin, Yu-Peng Tsai, Cheng-Ting Chen
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Publication number: 20200271873Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.Type: ApplicationFiled: February 21, 2019Publication date: August 27, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
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Publication number: 20200152616Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.Type: ApplicationFiled: January 12, 2020Publication date: May 14, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
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Patent number: 10566261Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: GrantFiled: March 29, 2018Date of Patent: February 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20200045777Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
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Patent number: 10535644Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.Type: GrantFiled: August 9, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
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Patent number: 10534353Abstract: A system for reducing processing defects during processing of a semiconductor wafer prior to back-grinding the wafer includes a table having one or more holes formed therein, wherein the table comprises at least one of a chuck table or a support table, wherein the holes are perpendicular to the surface upon which a pre-back-grinding (PBG) process occurs. The system further includes one or more sensors disposed in said holes for monitoring a parameter during the PBG process. The system further includes a computer-implemented process control tool coupled with the one or more sensors and configured to determine whether the PBG process will continue.Type: GrantFiled: October 3, 2013Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Fa Lu, Cheng-Ting Chen, James Hu, Chung-Shi Liu
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Publication number: 20200006191Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20200006308Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.Type: ApplicationFiled: August 9, 2018Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
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Patent number: 10512124Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.Type: GrantFiled: December 15, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu