Patents by Inventor Cheng-Ting Chung
Cheng-Ting Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170553Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.Type: ApplicationFiled: January 2, 2024Publication date: May 23, 2024Inventors: Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11987431Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.Type: GrantFiled: March 27, 2023Date of Patent: May 21, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
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Patent number: 11975741Abstract: An automated guided vehicle control system includes a commodity database, a historical shopping information acquisition module, a purchase-item prediction module, an automated guided vehicle database, an automated guided vehicle dispatch demand assessment module and an automated guided vehicle dispatch module. The historical shopping information acquisition module is utilized to retrieve the historical shopping information related to the customer, further to locate the instant predicted commodity to be purchased, and thereby to dispatch the suitable automated guided vehicle to the waiting area of the customer. Further, the historical shopping information is evaluated to provide the commodity type options for the customer to select, to locate the commodity type to be purchased, and thereby to organize the automated navigation path for the automated guided vehicle to travel along to reach the assigned commodity display area.Type: GrantFiled: August 3, 2021Date of Patent: May 7, 2024Assignee: TECO ELECTRIC & MACHINERY CO., LTD.Inventors: Yi-Ting Li, Cheng-Yun Chung
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Publication number: 20240110030Abstract: A styrene-modified polyethylene-based expandable resin particle is provided, which comprise a polyethylene resin and a polystyrene resin, wherein a content of the polyethylene resin ranges from 5 wt % to 30 wt % and a content of the polystyrene resin ranges from 70 wt % to 95 wt % based on 100 wt % of the polyethylene resin and the polystyrene resin, wherein the expandable resin particle comprises a xylene insoluble matter and an acetone insoluble matter, and a ratio of a content of the xylene insoluble matter to a content of the acetone insoluble matter ranges from 0.01 to 5. In addition, an expanded resin particle and a foamed resin molded article prepared by the aforesaid expandable resin particle are also provided. Furthermore, a method for manufacturing the aforesaid expandable resin particle is also provided.Type: ApplicationFiled: September 28, 2023Publication date: April 4, 2024Inventors: Han-Liou YI, Yao-Hsien CHUNG, Cheng-Ting HSIEH, Yu-Pin LIN, Keng-Wei HSU
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Patent number: 11948989Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng
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Publication number: 20240072052Abstract: In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.Type: ApplicationFiled: January 6, 2023Publication date: February 29, 2024Inventors: Cheng-Ting Chung, Yi-Bo Liao, Jin Cai
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Publication number: 20240072046Abstract: A semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. The gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. The electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. Methods for manufacturing the semiconductor structure are also disclosed.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ting CHUNG, Li-Zhen YU, Jin CAI
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Patent number: 11908942Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.Type: GrantFiled: July 7, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
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Patent number: 11862701Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively. The first and second S/D epitaxial features have a first conductivity type. The semiconductor device also includes a stack of second channel layers stacked over the first channel layers and third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively. The third and fourth S/D epitaxial features have a second conductivity type. A total active channel layer number of the first channel layers is different from that of the second channel layers.Type: GrantFiled: May 27, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
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Publication number: 20230411467Abstract: A semiconductor device includes a channel region, first and second S/D contacts, first and second S/D epitaxial regions, a gate structure, and a gate contact. The channel region includes a first surface, a second surface opposite to the first surface, and a sidewall connected to the first surface and the second surface. The first S/D contact is disposed over the first surface of the channel region, the second S/D contact is disposed underneath the second surface of the channel region, the first S/D epitaxial region underlies the first S/D contact and overlies the first surface of the channel region, and the second S/D epitaxial region overlies the second S/D contact and underlies the second surface of the channel region. The gate structure surrounds the sidewall of the channel region, and the gate contact is disposed in proximity to the second S/D contact and lands on the gate structure.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ting Chung, Yu-Xuan Huang, Hou-Yu Chen, Jin Cai
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Patent number: 11837538Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.Type: GrantFiled: April 18, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Bo Liao, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng, Kuan-Lun Cheng
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Publication number: 20230387001Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Bo LIAO, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng, Kuan-Lun Cheng
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Publication number: 20230378363Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung, Chih-Hao Wang
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Publication number: 20230369504Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Cheng-Ting Chung, Ching-Wei Tsai, Hou-Yu Chen
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Publication number: 20230352567Abstract: A semiconductor structure includes a stack of at least two semiconductor channel layers, a gate structure wrapping each of the semiconductor channel layers, and first and second source/drain (S/D) features disposed on opposing sides of the gate structure. The first and second S/D features, the semiconductor channel layers, and the gate structure are at a frontside of the semiconductor structure. At least one of the semiconductor channel layers is free of contact with the first S/D feature.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Cheng-Ting Chung, Kuan-Lun Cheng
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Publication number: 20230335617Abstract: A method includes forming a dielectric layer over a substrate; forming a carbon nanotube (CNT) over the dielectric layer; forming a dummy gate structure over the CNT; forming gate spacers on opposite sidewalls of the dummy gate structure; forming source/drain epitaxy structures on opposite sides of the dummy gate structure and in contact with opposite sidewalls of the CNT; replacing the dummy gate structure with a metal gate structure; and forming source/drain contacts over the source/drain epitaxy structures, respectively.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mahaveer Sathaiya DHANYAKUMAR, Cheng-Ting CHUNG, Chien-Hong CHEN, Jin CAI, Chung-Wei WU
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Publication number: 20230317674Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.Type: ApplicationFiled: January 6, 2023Publication date: October 5, 2023Inventors: Che Chi SHIH, Cheng-Ting CHUNG, Han-Yu LIN, Wei-Yen WOON, Szuya LIAO
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Patent number: 11777033Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.Type: GrantFiled: December 23, 2020Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung, Chih-Hao Wang
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Patent number: 11757042Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.Type: GrantFiled: February 14, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Cheng-Ting Chung, Ching-Wei Tsai, Hou-Yu Chen
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Publication number: 20230268391Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Chi-Yi CHUANG, Cheng-Ting CHUNG, Hou-Yu CHEN, Kuan-Lun CHENG