Patents by Inventor Cheng-Wei Luo
Cheng-Wei Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929196Abstract: A method of making a slow wave inductive structure includes depositing a first dielectric layer over a first substrate. The method further includes forming a first conductive winding in the first dielectric layer. The method further includes bonding a second substrate to the first dielectric layer, wherein the second substrate is physically separated from the first conductive winding, and the second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm. The method further includes depositing a second dielectric layer over the second substrate. The method further includes forming a second conductive winding in the second dielectric layer, wherein the second substrate is physically separated from the second conductive winding.Type: GrantFiled: August 5, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
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Patent number: 11916098Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.Type: GrantFiled: December 28, 2020Date of Patent: February 27, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
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Patent number: 11848290Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.Type: GrantFiled: March 31, 2021Date of Patent: December 19, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
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Patent number: 11830648Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.Type: GrantFiled: September 17, 2020Date of Patent: November 28, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chieh-Pin Chang, Cheng-Wei Luo, Kai-Yi Huang, Ta-Hsun Yeh
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Publication number: 20230282407Abstract: An inductor device includes a first wire and a second wire. The first wire includes a first sub-wire and a second sub-wire. The first sub-wire is disposed in a first area. The second sub-wire is disposed in a second area, and the first sub-wire and the second sub-wire are located on different layers. The second wire includes a third sub-wire and a fourth sub-wire. The third sub-wire is disposed in the second area, and located below the second sub-wire. The fourth sub-wire is disposed in the first area, the third sub-wire and the fourth sub-wire are located on different layers, and the fourth sub-wire is located above the first sub-wire.Type: ApplicationFiled: June 7, 2022Publication date: September 7, 2023Inventors: Chieh-Pin CHANG, Cheng-Wei LUO
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Patent number: 11699656Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first inductor, a second inductor and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first gate layer. The first inductor is over the first shielding layer. The second inductor is below the first substrate. The first IMD layer is between the first substrate and the first shielding layer.Type: GrantFiled: July 1, 2021Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
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Patent number: 11682518Abstract: An inductor device includes a first coil and a second coil. The first coil is wound into a plurality of first circles, and the second coil is wound into a plurality of second circles. At least two of the second circles are interlaced with at least two of the first circles on a first side. The at least two of the second circles are disposed adjacent to each other on the first side. At least one of the first circles is only interlaced with at least one of the second circles on a second side. At least another one of the first circles is only interlaced with at least another one of the second circles on the second side.Type: GrantFiled: June 3, 2020Date of Patent: June 20, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chieh-Pin Chang, Cheng-Wei Luo, Kai-Yi Huang, Ta-Hsun Yeh
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Publication number: 20230154670Abstract: An inductor device includes a first winding, a second winding, a first connecting structure and a second connecting structure. The first winding includes a first coil and a second coil. The second winding includes a third coil and a fourth coil, the third coil is overlapped with the first coil, and the fourth coil is overlapped with the second coil. The first connecting structure includes a first crossing structure and a second crossing structure. The first crossing structure has a first crossing point and is configured to couple the first coil and the second coil. The second crossing structure has a second crossing point and is configured to couple the third coil and the fourth coil. The first crossing point is not overlapped with the second crossing point. The second connecting structure is configured to couple the second coil and the third coil.Type: ApplicationFiled: September 15, 2022Publication date: May 18, 2023Inventor: Cheng-Wei LUO
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Publication number: 20230144972Abstract: An inductor device is disclosed herein. An electrical device is disposed in a first area of the inductor device, and the inductor device includes a first trace and a second trace. The first trace is disposed in a second area. The second trace is disposed in the second area, and coupled to the first trace. The second area is disposed an outer side of the first area, and the first area and the second area are not overlapped with each other.Type: ApplicationFiled: September 21, 2022Publication date: May 11, 2023Inventors: Cheng-Wei LUO, Hsiao-Tsung YEN
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Patent number: 11610714Abstract: A slow wave inductive structure includes a first substrate. The slow wave inductive structure further includes a first conductive winding over the first substrate. The slow wave inductive structure further includes a second substrate over the first substrate, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m, and the second substrate comprises polysilicon or doped silicon. The slow wave inductive structure further includes a second conductive winding on an opposite side of the second substrate from the first conductive winding.Type: GrantFiled: November 20, 2019Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
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Publication number: 20220310511Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.Type: ApplicationFiled: June 6, 2022Publication date: September 29, 2022Inventors: Hsiao-Tsung YEN, Chin-Wei KUO, Cheng-Wei LUO, Kung-Hao LIANG
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Patent number: 11450599Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.Type: GrantFiled: January 8, 2021Date of Patent: September 20, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
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Publication number: 20220270812Abstract: An inductor and an integrated circuit are provided. The inductor includes a first coil, a second coil, and a third coil. The first coil has a first input terminal and a first output terminal, and the first coil is winded in a first direction from the first input terminal to the first output terminal. The second has a second input terminal and a second output terminal, and the second coil is winded in a second direction which is opposite to the first direction from the second input terminal to the second output terminal. The third has a third input terminal and a third output terminal, and the third input terminal is connected to the first input terminal and the second input terminal.Type: ApplicationFiled: April 13, 2021Publication date: August 25, 2022Inventors: Chieh-Pin CHANG, Cheng-Wei LUO, Kai-Yi HUANG, Ta-Hsun YEH
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Publication number: 20220208437Abstract: The present invention discloses an inductor apparatus. Each of a first section of a second and a fourth quadrant loops are bridged to a first section of a former quadrant loop and are bridged to a third section to a second section of a diagonal quadrant loop. Each of a second section of the second and the fourth quadrant loops are coupled to a third section of the diagonal quadrant loop, and to the second section of a former quadrant loop. A first section of a third quadrant loop is coupled to a first section of the fourth quadrant loop, and to a third section of the first quadrant loop. The second section of the third quadrant loop is coupled to a second section of the fourth quadrant loop and to a third section of the third quadrant loop, and to a third section of the first quadrant loop.Type: ApplicationFiled: December 15, 2021Publication date: June 30, 2022Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
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Patent number: 11355432Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.Type: GrantFiled: May 26, 2020Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
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Patent number: 11302470Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.Type: GrantFiled: December 3, 2019Date of Patent: April 12, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
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Publication number: 20220077083Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.Type: ApplicationFiled: March 31, 2021Publication date: March 10, 2022Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
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Patent number: 11250985Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.Type: GrantFiled: December 3, 2019Date of Patent: February 15, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
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Publication number: 20210366643Abstract: A method of making a slow wave inductive structure includes depositing a first dielectric layer over a first substrate. The method further includes forming a first conductive winding in the first dielectric layer. The method further includes bonding a second substrate to the first dielectric layer, wherein the second substrate is physically separated from the first conductive winding, and the second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm. The method further includes depositing a second dielectric layer over the second substrate. The method further includes forming a second conductive winding in the second dielectric layer, wherein the second substrate is physically separated from the second conductive winding.Type: ApplicationFiled: August 5, 2021Publication date: November 25, 2021Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
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Publication number: 20210349644Abstract: A device for managing storage resources includes a plurality of servers with storage devices, a setting module, a first establishing module, and a second establishing module. The setting module includes a plurality of first storage devices in each server to be a virtual hard disk. When any other storage device of a server is damaged, the storage managing device maps the virtual hard disk with a new storage device and establishes a logical storage device, to perform data access operations on the logical storage device. A related method and a related non-transitory storage medium are also provided.Type: ApplicationFiled: May 28, 2020Publication date: November 11, 2021Inventor: CHENG-WEI LUO