Patents by Inventor CHENG-YAN JI

CHENG-YAN JI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948991
    Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Patent number: 11903180
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Yan Ji, Wei-Tong Chen
  • Publication number: 20230413533
    Abstract: The present application provides a method of fabricating a semiconductor device. The method includes steps of forming a transistor in a substrate; depositing an insulative layer on the substrate; forming a first trench penetrating through the insulative layer to expose a portion of a first impurity region of the transistor; performing a first cyclic process comprising a first sequence of a first deposition step and a first removal step to deposit a conductive material in the first trench until a height of the conductive material in the first trench exceeds a predetermined height; filling the first trench with the conductive material after the first cyclic process; forming a storage capacitor contacting the first conductive feature; and depositing an isolation layer to cover the insulative layer and the storage capacitor.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 21, 2023
    Inventors: CHENG-YAN JI, CHU-HSIANG HSU, JING HSU
  • Publication number: 20230402313
    Abstract: The present application provides a method of fabricating a conductive feature. The method of fabricating the conductive feature includes steps of depositing an insulative layer on a substrate, forming a trench in the insulative layer, performing a cyclic process comprising a sequence of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step has been performed is equal to a first preset number of times and a number of the times the removal step has been performed is equal to a second preset number of times, and filling the trench with the conductive material after the cyclic process.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: CHENG-YAN JI, CHU-HSIANG HSU, JING HSU
  • Patent number: 11830762
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen-Hao Lien, Cheng-Yan Ji, Chu-Hsiang Hsu
  • Publication number: 20230335395
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: depositing a first semiconductor layer on an inner surface of a trench of a substrate; depositing a second semiconductor layer on the first semiconductor layer on the inner surface of the trench of the substrate, in which a dopant concentration of the first semiconductor layer is less than a dopant concentration of the second semiconductor layer; and depositing a third semiconductor layer on the second semiconductor layer to fill the trench of the substrate, in which a dopant concentration of the third semiconductor layer is less than the dopant concentration of the second semiconductor layer.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Kai Hung LIN, Cheng Yan JI
  • Publication number: 20230301055
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: CHENG-YAN JI, WEI-TONG CHEN
  • Publication number: 20230299161
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a word line structure. The semiconductor substrate has an active region. The word line structure is disposed in the active region of the semiconductor substrate. The word line structure includes a first work function layer, a second work function layer, and a buffer structure. The second work function layer is on the first work function layer. The buffer structure is between the first work function layer and the second work function layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: CHENG-YAN JI, WEI-TONG CHEN
  • Publication number: 20230187266
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: CHEN-HAO LIEN, CHENG-YAN JI, CHU-HSIANG HSU
  • Publication number: 20230187520
    Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Chen-Hao LIEN, Cheng-Yan JI, Chu-Hsiang HSU