Patents by Inventor Cheng Yang

Cheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155082
    Abstract: A body-worn camera and an operation method thereof are provided, and the body-worn camera a central processing unit, a video recording module, a turntable, and a main button. The video recording module is electrically connected to the central processing unit. The turntable is electrically connected to the central processing unit. The main button is electrically connected to the central processing unit. After the video recording module completes recording a video, when the central processing unit receives a category mode signal from the turntable and receives a category name confirmation signal from the main button, the central processing unit executes a video tagging program, and the video tagging program saves a corresponding relationship between a category name and the video.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 9, 2024
    Inventors: HSIEN-YANG CHIANG, TA-WEI CHANG, CHENG-LIANG HUANG, YEH-SHENG CHEN
  • Publication number: 20240152815
    Abstract: A solution for generating a positive sample pair of a contrastive learning model is provided. In one method, a first data segment and a second data segment are respectively obtained from a first data sequence in plurality of data sequences for training the contrastive learning model, the first data sequence comprising a plurality of data frames. A data frame is selected from a second data sequence in the plurality of data sequences. A third data segment is generated based on the second data segment and the data frame. A positive sample pair for training the contrastive learning model is determined using the first data segment and the third data segment. In this way, positive samples that are more difficult to distinguish can be provided, thereby increasing the accuracy of the contrastive learning model and improving the training efficiency and accuracy of downstream models.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Inventors: Hao WU, Cheng YANG
  • Publication number: 20240153719
    Abstract: An operation-indication mode switching structure, a circuit, and a method for operating the same are provided. The operation-indication mode switching structure is disposed on a housing of a device, and includes a switching mechanism that is used to switch multiple operation-indication modes. The switching mechanism is selectively connected with one of multiple signal terminals. When the switching mechanism is manipulated to switch to one of the operation-indication modes, a control unit of the device receives an operation-indication mode switching signal generated by the switching mechanism conducting or circuit-shorting one of the multiple signal terminals. A corresponding operation-indication mode that is a covert mode, a stealth mode, or a normal mode can be determined. The control unit is used to control an indication function of the device according to the operation-indication mode that is switched to.
    Type: Application
    Filed: July 18, 2023
    Publication date: May 9, 2024
    Inventors: HSIEN-YANG CHIANG, TA-WEI CHANG, CHENG-LIANG HUANG, YEH-SHENG CHEN
  • Publication number: 20240153307
    Abstract: A sitting posture detection method includes: identifying an input image to generate a face frame under detection and a human frame under detection of a person under detection; calculating a plurality of face angles of the face frame under detection; calculating a plurality of bone feature point coordinates of the human frame under detection; and generating standard sitting posture data according to the face angles and the bone feature point coordinates, and determining a sitting posture of the person under detection according to the face angles, the bone feature point coordinates and the standard sitting posture data.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 9, 2024
    Inventors: Jing-Song RAO, Xiang-Wei LIN, Fei-Yang TONG, Cheng-Wei ZHENG
  • Publication number: 20240151020
    Abstract: A foldable nozzle assembly and a bidet are provided. The foldable nozzle assembly includes a nozzle body. The nozzle body is equipped with a nozzle base, and a limiting component is installed between the nozzle base and the nozzle body. A rotational component on the nozzle base allows for the pivotal attachment of a rotating base, which supports a nozzle. The nozzle can be folded onto the nozzle base using the limiting component and the rotational component, enabling the foldable functionality of the bidet nozzle, reducing space occupation, and facilitating storage. The invention features a simple structure, ease of use, and practicality.
    Type: Application
    Filed: November 5, 2023
    Publication date: May 9, 2024
    Inventors: Xiaomin LUO, Shaojie SHI, Cheng YANG, Weihao ZHENG
  • Patent number: 11976105
    Abstract: The present application provides antibody-TCR chimeric constructs comprising an antibody moiety that specifically binds to a target antigen fused to a TCRM capable of recruiting at least one TCR-associated signaling module. Also provided are methods of making and using these constructs.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 7, 2024
    Assignee: EUREKA THERAPEUTICS, INC.
    Inventors: Jingwei Lu, Zhiyuan Yang, Cheng Liu, Hong Liu, Yiyang Xu, Su Yan, Vivien Wai-Fan Chan, Lucas Horan
  • Patent number: 11977249
    Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Tse Tang, Chewn-Pu Jou, Lan-Chou Cho, Ming Yang Jung, Tai-Chun Huang
  • Patent number: 11977335
    Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 7, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
  • Patent number: 11978677
    Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240140023
    Abstract: The present disclosure provides a method for photo-curing 4D printing of a multi-layer structure with an adjustable shape recovery speed, and a multi-layer structure printed thereby. The multi-layer structure printed by the method for photo-curing 4D printing of the multi-layer structure with the adjustable shape recovery speed includes a plurality of deformation units sequentially connected in series, and each of the plurality of the deformation units includes two slow layers, a fast layer, and a transition layer; and the fast layer is arranged between the two slow layers, and the transition layer is arranged between at least one of the two slow layers and the fast layer. In the present disclosure, a low cross-linking layer is doped with a nanocarbon light-absorbing material to solve the problem that the low cross-linking layer is prone to over-curing when a high cross-linking layer is printed on the low cross-linking layer.
    Type: Application
    Filed: December 16, 2022
    Publication date: May 2, 2024
    Applicant: Jiangsu University
    Inventors: Shu HUANG, Hang ZHANG, Jianzhong ZHOU, Jie SHENG, Jiean WEI, Hongwei YANG, Cheng WANG, Mingyuan SHAN
  • Publication number: 20240144007
    Abstract: A method of contrastive learning comprises: determining, based on a model construction criterion, a first encoder for a first modality and a second encoder for a second modality; constructing a first contrastive learning model, the first contrastive learning model comprising the first encoder and a third encoder for the second modality, and a model capacity of the third encoder being greater than a model capacity of the second encoder; performing pre-training of the first contrastive learning model based on a first training dataset for the first modality and the second modality; and providing the pre-trained first encoder in the pre-trained first contrastive learning model for a downstream task. Because only the model capacity of one encoder is increased in the pre-training stage, model performance may be improved without increasing model training overhead during downstream task fine-tuning and model running overhead during model application.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 2, 2024
    Inventors: Hao Wu, Boyan Zhou, Quan Cui, Cheng Yang
  • Publication number: 20240146582
    Abstract: An information encoding control method includes: receiving first configuration information, where the first configuration information is used to configure N groups of parameters of N artificial intelligence (AI) encoders or an AI decider, and the AI decider is configured to determine an AI encoder that is in the N AI encoders and to which first information is applicable, and/or is configured to determine that none of the N AI encoders is applicable to encoding the first information; and sending first indication information to a network device, where the first indication information indicates that a first encoder is used for encoding the first information, the first encoder is determined based on the first configuration information and the first information, and the first encoder is an encoder in the N AI encoders, or is a second encoder different from the N AI encoders.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 2, 2024
    Inventors: Sihai WANG, Xueru LI, Cheng QIN, Rui YANG
  • Publication number: 20240144100
    Abstract: Methods, apparatuses, a device, and a medium for training a contrastive learning model are provided. In a method, a plurality of sample sets for training the contrastive learning model are obtained, and the plurality of sample sets comprises a first sample set and a second sample set. A first target sample set is selected from the first sample set and the second sample set according to a predetermined rule. A first set of samples are determined based on the first target sample set according to a predefined batch size. The contrastive learning model is trained using the first set of samples. In this way, on the one hand, performance degradation of the contrastive learning model due to sample set bias may be avoided; on the other hand, a forgetting problem in the training process may be alleviated.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Hao Wu, Boyan Zhou, Quan Cui, Cheng Yang
  • Publication number: 20240145389
    Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.
    Type: Application
    Filed: July 28, 2023
    Publication date: May 2, 2024
    Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
  • Publication number: 20240140007
    Abstract: The present invention relates to the technical field of chip package, in particular to a semiconductor package injection molding mold, a semiconductor package injection molding device and a semiconductor package injection molding method. The semiconductor package injection molding mold includes a bottom mold and a top mold. The upper surface of the bottom mold is fitted with the lower surface of a substrate to form a semiconductor package structure; the top mold is matched with the bottom mold; the top mold has a cavity; the cavity is oriented toward the upper surface of the substrate and is used to accommodate a plastic package layer formed on the upper surface of the substrate; through holes that penetrate through the bottom mold are formed at positions corresponding to the substrate in the bottom mold; and the through holes are connected with an external pressure source.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 2, 2024
    Applicant: JCET Management Co., Ltd.
    Inventor: Cheng Yang
  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20240143083
    Abstract: An interactive simulation system with a stereoscopic image and a method for operating the system are provided. The system includes a three-dimensional display and a control host. The stereoscopic image display is used to display a stereoscopic image. The system includes an interactive sensor that is used to sense gesture of a user or an action that the user manipulates a haptic device so as to produce sensing data. In the meantime, the system detects eye positions of the user. The changes of coordinates with respect to the gesture or the haptic device can be determined and referred to for forming a manipulation track. An interactive instruction can be determined. The stereoscopic image can be updated according to the interactive instruction and the eye positions of the user.
    Type: Application
    Filed: February 15, 2023
    Publication date: May 2, 2024
    Inventors: YUNG-CHENG CHENG, CHUN-HSIANG YANG
  • Patent number: 11973040
    Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
  • Publication number: 20240133928
    Abstract: An abnormal detection circuit is provided. The abnormal detection circuit includes a conversion circuit, a voltage detection circuit, and a warning circuit. The conversion circuit receives a three-phase alternating current (AC) power and converts the three-phase AC power into a driving power. The voltage detection circuit detects each phase of the three-phase AC power. When a voltage value of at least one phase AC power of the three-phase AC power is abnormal, the voltage detection circuit uses the driving power to output at least one control signal corresponding to the abnormality. The warning circuit is driven by receiving the driving power and outputs at least one warning signal corresponding to the abnormality in response to the at least one control signal.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 25, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Wen-Cheng Liang, Teng-Chieh Yang, Chi-Tien Sun
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin