Patents by Inventor Cheng-Yen Chang
Cheng-Yen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162084Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: ApplicationFiled: January 26, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen HUANG, Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cheng-Chin LEE, Shau-Lin SHUE, Hsiao-Kang CHANG
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Publication number: 20240153843Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Patent number: 11942451Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
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Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
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Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
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Patent number: 11915994Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Patent number: 8897548Abstract: A low-complexity method of converting 2D images/videos into 3D ones includes the steps of identifying whether each pixel in one of the frames is an edge feature point; locating at least two vanishing lines in the frame according to the edge feature point; categorizing the frame into the one of close-up photographic feature, of landscape feature, and of vanishing-area feature; if the frame is identified to have the vanishing-area feature or the landscape feature to generate a GDM; and apply a modificatory procedure to the GDM to generate a final depth information map; if the frame is identified to have the close-up photographic feature, distinguish between a foreground object and a background information in the frame and define the depth of field to generate the final depth information map.Type: GrantFiled: April 2, 2013Date of Patent: November 25, 2014Assignee: National Chung Cheng UniversityInventors: Jiun-In Guo, Jui-Sheng Lee, Cheng-An Chien, Jia-Hou Chang, Cheng-Yen Chang
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Publication number: 20140294287Abstract: A low-complexity method of converting 2D images/videos into 3D ones includes the steps of identifying whether each pixel in one of the frames is an edge feature point; locating at least two vanishing lines in the frame according to the edge feature point; categorizing the frame into the one of close-up photographic feature, of landscape feature, and of vanishing-area feature; if the frame is identified to have the vanishing-area feature or the landscape feature to generate a GDM; and apply a modificatory procedure to the GDM to generate a final depth information map; if the frame is identified to have the close-up photographic feature, distinguish between a foreground object and a background information in the frame and define the depth of field to generate the final depth information map.Type: ApplicationFiled: April 2, 2013Publication date: October 2, 2014Applicant: National Chung Cheng UniversityInventors: Jiun-In GUO, Jui-Sheng LEE, Cheng-An CHIEN, Jia-Hou CHANG, Cheng-Yen Chang