Patents by Inventor Cheng-Yi Lee
Cheng-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002714Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.Type: GrantFiled: August 9, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Kuan-Yu Wang, Cheng-Lung Hung, Chi-On Chui
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Publication number: 20240177998Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.Type: ApplicationFiled: February 7, 2024Publication date: May 30, 2024Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Publication number: 20240175317Abstract: A blind lifting control module includes a transmitting wheel, an anti-backward unit and a driving unit disposed to a supporting unit. The transmitting wheel for connecting a blind reeled horizontal axle has a wheel ratchet portion meshable with a corresponding reel ratchet portion of a driving reel of the driving unit. The anti-backward unit has a torsion spring operable and deformable relative to the transmitting wheel. A pull cord is reeled on the driving reel and has a free end passing through a thrust member and a hindering member, and is pulled to shift the torsion spring to a released state to permit lowering of a blind. The thrust member is turned by pulling of the pull cord to thrust the driving reel to mesh with the transmitting wheel for lifting the blind.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: Cheng-Hung LEE, Lung-Yi CHIANG
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Patent number: 11990100Abstract: An e-paper identification card system including an e-paper identification card and a data updating apparatus is provided. The e-paper identification card is configured to display first image information. The data updating apparatus is electrically connected to the e-paper identification card. The data updating apparatus is configured to update the e-paper identification card according to the first image information to drive the e-paper identification card to display second image information. In addition, an e-paper identification card is also provided.Type: GrantFiled: January 12, 2023Date of Patent: May 21, 2024Assignee: E Ink Holdings Inc.Inventors: Chih-Chun Chen, Huei-Chuan Lee, Cheng-Hsien Lin, Shuo-En Lee, Kai-Yi Cho
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Patent number: 11990510Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.Type: GrantFiled: July 26, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
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Publication number: 20240162303Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Publication number: 20240145543Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yi LEE, Cheng-Lung HUNG, Chi On CHUI
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Patent number: 11955528Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.Type: GrantFiled: October 11, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi-On Chui
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Publication number: 20240113183Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi On Chui
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Patent number: 11942376Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.Type: GrantFiled: August 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
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Patent number: 11935890Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.Type: GrantFiled: April 11, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
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Patent number: 11935754Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.Type: GrantFiled: June 30, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Patent number: 11927058Abstract: A blind lifting control module includes a transmitting wheel, an anti-backward unit and a driving unit disposed to a supporting unit. The transmitting wheel for connecting a blind reeled horizontal axle has ratchet portions respectively meshable with corresponding ratchet portions of an anti-backward wheel and a driving reel. A pull cord is reeled on the driving reel and has a free end passing through a thrust member and a hindering member, and is pulled to release the anti-backward wheel to permit lowering of a blind. The thrust member is turned by pulling of the pull cord to thrust the driving reel to mesh with the transmitting wheel for lifting the blind.Type: GrantFiled: October 19, 2021Date of Patent: March 12, 2024Assignee: SYNCPROTO CO., LTD.Inventors: Cheng-Hung Lee, Lung-Yi Chiang
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Patent number: 11929422Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: GrantFiled: July 29, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11923240Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate. The first transistor includes a first gate structure, and the second transistor includes a second gate structure. The first gate structure includes a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially formed on the substrate. The second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate. The first capping layer and the second capping layer comprise materials having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.Type: GrantFiled: July 27, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Da-Yuan Lee
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Patent number: 11916114Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.Type: GrantFiled: June 30, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
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Patent number: 11500214Abstract: An augmented reality (AR) device includes a main body, a support element, and a lens module. The main body includes a base, a projector, and a first pivot portion. The projector is pivoted to the base by using the first pivot portion, so that the projector is capable of rotating relative to the base by using the first pivot portion as a first rotation axis. The support element is pivoted to a first end portion of the base and is configured to wear on a head of a user. The lens module is pivoted to a second end portion of the base and the second end portion is opposite to the first end portion. The lens module is capable of rotating relative to the base and being overlapped under the base. Through a rotatable and foldable accommodation structure, the augmented reality device is easier to be carried and accommodated.Type: GrantFiled: March 4, 2020Date of Patent: November 15, 2022Assignee: PEGATRON CORPORATIONInventors: Chih-Cheng Chung, Hsiao-Cheng Chen, Cheng-Yi Lee
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Patent number: 11288360Abstract: Using a first key, an encrypted file fingerprint is decrypted, the decrypting resulting in a decrypted file fingerprint. Using a hash function on a script file, a script file fingerprint is computed, the script file intended to be executed by an interpreter. Responsive to the script file fingerprint matching the decrypted file fingerprint, the script file is executed.Type: GrantFiled: March 4, 2020Date of Patent: March 29, 2022Assignee: KYNDRYL, INC.Inventors: Constantin Mircea Adam, Richard Jay Cohen, Jeffrey Edward Lammers, Cheng Yi Lee, Brian Peterson, Maja Vukovic, Xiongfei Wei
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Publication number: 20210279326Abstract: Using a first key, an encrypted file fingerprint is decrypted, the decrypting resulting in a decrypted file fingerprint. Using a hash function on a script file, a script file fingerprint is computed, the script file intended to be executed by an interpreter. Responsive to the script file fingerprint matching the decrypted file fingerprint, the script file is executed.Type: ApplicationFiled: March 4, 2020Publication date: September 9, 2021Applicant: International Business Machines CorporationInventors: Constantin Mircea Adam, Richard Jay Cohen, Jeffrey Edward Lammers, Cheng Yi Lee, Brian Peterson, Maja Vukovic, Xiongfei Wei
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Patent number: D922993Type: GrantFiled: August 8, 2018Date of Patent: June 22, 2021Assignee: PEGATRON CORPORATIONInventors: Chih-Cheng Chung, Hsiao-Cheng Chen, Cheng-Yi Lee