Patents by Inventor Cheng Yi-Lung

Cheng Yi-Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406609
    Abstract: In a manufacturing method of an opening structure, a multi-layer structure including alternately stacked conductive layers and first dielectric layers is formed on a substrate. The conductive layers in a first region are lower than those in a second region. A second dielectric layer covering the multi-layer structure is formed. A patterned mask layer is formed on the second dielectric layer. A first filling layer covering the second dielectric layer exposed by the patterned mask layer is formed in the second region. First openings exposing the conductive layers in the first region are formed by using the first filling layer and the patterned mask layer as a mask. The first filling layer is removed. A second filling layer filling the first openings is formed. Second openings exposing the conductive layers in the second region are formed by using the second filling layer and the patterned mask layer as a mask.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 2, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Cheng-Yi Lung
  • Publication number: 20160086968
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of stack structures, and a plurality of support layers. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of conductor layers and a plurality of dielectric layers. The dielectric layers and the conductor layers are disposed alternately. The support layers are disposed in the stack structures respectively.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 24, 2016
    Inventors: Zu-Sing Yang, Cheng-Yi Lung
  • Patent number: 9252153
    Abstract: A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: February 2, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Yi Lung, An-Chyi Wei, Ta Hung Yang
  • Publication number: 20030068444
    Abstract: A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 10, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Yoo Ming-Hwa, Cheng Yi-Lung, Wu Szu-An, Wang Ying-Lang