Abstract: A multiplier for calculating a multiplication of a first fixed point number and a second fixed point number comprises a converter and a restoration circuit. The converter is configured to convert the first fixed point number to a sign, a mantissa, and an exponent. At least one of a bit width of the sign, a bit width of the mantissa, and a bit width of the exponent is dynamically configured based on a position of a layer associated with the first fixed point number in a neural network, a position of a pixel in an input feature map associated with the first fixed point number, and/or a channel associated with the first fixed point number. The restoration circuit is configured to calculate the multiplication based on the sign, the mantissa, the exponent, and the second fixed point number.

Abstract: A multiplier for calculating a multiplication of a first fixed point number and a second fixed point number comprises a converter and a restoration circuit. The converter is configured to convert the first fixed point number to a sign, a mantissa, and an exponent. At least one of a bit width of the sign, a bit width of the mantissa, and a bit width of the exponent is dynamically configured based on a position of a layer associated with the first fixed point number in a neural network, a position of a pixel in an input feature map associated with the first fixed point number, and/or a channel associated with the first fixed point number. The restoration circuit is configured to calculate the multiplication based on the sign, the mantissa, the exponent, and the second fixed point number.

Abstract: A graphics processing unit (GPU) includes programmable shader hardware and grouping hardware. The grouping hardware receives pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive. The grouping hardware also groups the pixels into a set of groups having a sequential order. None of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups. The programmable shader hardware performs order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel. The programmable shader hardware also performs order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.

Abstract: A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.

Abstract: A graphics processing unit (GPU) includes programmable shader hardware and grouping hardware. The grouping hardware receives pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive. The grouping hardware also groups the pixels into a set of groups having a sequential order. None of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups. The programmable shader hardware performs order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel. The programmable shader hardware also performs order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.

Abstract: A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.