Patents by Inventor Cheng-Yuan Lai
Cheng-Yuan Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Publication number: 20240095168Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.Type: ApplicationFiled: August 17, 2023Publication date: March 21, 2024Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
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Publication number: 20240095177Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.Type: ApplicationFiled: August 17, 2023Publication date: March 21, 2024Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
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Patent number: 11935825Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.Type: GrantFiled: August 28, 2019Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
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Patent number: 9223164Abstract: A display includes a display medium layer and a dielectric layer disposed at a side of the display medium layer. The composition of the dielectric layer includes at least a humectant for decreasing the electric resistivity of the dielectric layer and stabilizing the electric performance of the display.Type: GrantFiled: August 2, 2013Date of Patent: December 29, 2015Assignee: SiPix Technology, Inc.Inventors: Cheng-Yuan Lai, Hui Chen, Jung-An Cheng, Wei-Ho Ting, Yu Li, Hongmei Zang, Ming Wang, Zoran Topalovic, Tyau-Jeen Lin
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Publication number: 20150036206Abstract: A display includes a display medium layer and a dielectric layer disposed at a side of the display medium layer. The composition of the dielectric layer includes at least a humectant for decreasing the electric resistivity of the dielectric layer and stabilizing the electric performance of the display.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Applicant: SiPix Technology, Inc.Inventors: Cheng-Yuan Lai, Hui Chen, Jung-An Cheng, Wei-Ho Ting, Yu Li, Hongmei Zang, Ming Wang, Zoran Topalovic, Tyau-Jeen Lin
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Patent number: 6716676Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.Type: GrantFiled: September 19, 2002Date of Patent: April 6, 2004Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien
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Publication number: 20030020151Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.Type: ApplicationFiled: September 19, 2002Publication date: January 30, 2003Applicant: Siliconware Precision Industries Co., LtdInventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien
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Patent number: 6472741Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on he substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced beat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.Type: GrantFiled: July 14, 2001Date of Patent: October 29, 2002Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien
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Patent number: 6462405Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.Type: GrantFiled: July 18, 2001Date of Patent: October 8, 2002Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Yuan Lai, Chien-Ping Huang
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Patent number: 6400014Abstract: The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plate has a top surface exposed outside a resin body used for encapsulating the chip and the heat sink, and a bottom surface opposed to the top surface. The planar plate further has a thick portion formed on the bottom surface relative to the position of the chip, wherein there is a gap formed between the end surface of the thick portion and the chip to prevent the heat sink from directly contacting with the chip, and an end surface of the thick portion has a plurality of flow channels formed along the flowing direction of the molding gate to avoid the formation of void in the gap so as to increase the yield rate of products.Type: GrantFiled: January 13, 2001Date of Patent: June 4, 2002Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-ping Huang, Cheng-Yuan Lai, Tzu-Yi Tien, Chih-Ming Huang
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Publication number: 20020053724Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.Type: ApplicationFiled: July 18, 2001Publication date: May 9, 2002Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Yuan Lai, Chien-Ping Huang
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Publication number: 20010040300Abstract: A semiconductor package having a lead frame is provided in which the lead frame has a plurality of leads and a die pad for mounting a semiconductor die. The die pad is formed with at least one opening for exposing a portion of the surface of the semiconductor die. An encapsulant is formed to enclose the semiconductor die, portions of the leads and a portion of the die pad, while having a surface of the die pad to expose the form of the encapsulant. As a surface of the die pad is exposed to the exterior of the encapsulant, the opening formed on the die pad provides a thermal conduction path from the semiconductor die to the ambient, thereby enhancing the heat dissipation property of the semiconductor package.Type: ApplicationFiled: July 23, 1999Publication date: November 15, 2001Inventors: CHIEN-PING HUANG, CHENG-YUAN LAI
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Patent number: 6114752Abstract: A semiconductor package includes a lead frame having a die pad for a semiconductor chip to be mounted thereon. The die pad is surrounded by a plurality of leads for electrically connecting the semiconductor chip and has one opening formed to decrease the attaching area between the semiconductor chip and the die pad so as to prevent the occurrence of declamination. A base pad is provided to be coupled to the die pad in such a manner that the base pad is positioned underneath or above the die pad and has a bottom surface or a top surface to be exposed to the extension of a resin encapsulant for enclosing the semiconductor chip and a portion of the lead frame, allowing the base pad to serve as a heat dissipater for transferring heat of the semiconductor package to the ambient.Type: GrantFiled: August 25, 1999Date of Patent: September 5, 2000Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chion-Ping Huang, Cheng-Yuan Lai, Raymond Jao