Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.

Abstract: A testing system and method for an arithmetic logic unit are provided. The system includes: a control unit, a data providing unit, a first input unit, a second input unit, an arithmetic logic unit, an expected result unit, a comparator and a test result storage unit. The control unit controls the testing process. The data providing unit provides data for the first input unit, the second input unit and the expected result unit. The first input unit and the second input unit provide test data for the arithmetic logic unit. The arithmetic logic unit performs an operation and provides an operation result for the comparator. The expected result unit generates an expected result and provides the expected result of this round of testing for the comparator. The comparator compares the operation result with the expected result, and provides a comparison result for the test result storage unit.

Abstract: A method for assisting operations of a processor core coupled to a first memory and a second memory includes: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions, and creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the instructions, such that the processor core fetches the instructions from the second memory for execution. Filling the instructions further includes pre-fetching from the first memory to the second memory instruction segments containing the instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.

Abstract: A testing system and method for an arithmetic logic unit are provided. The system includes: a control unit, a data providing unit, a first input unit, a second input unit, an arithmetic logic unit, an expected result unit, a comparator and a test result storage unit. The control unit controls the testing process. The data providing unit provides data for the first input unit, the second input unit and the expected result unit. The first input unit and the second input unit provide test data for the arithmetic logic unit. The arithmetic logic unit performs an operation and provides an operation result for the comparator. The expected result unit generates an expected result and provides the expected result of this round of testing for the comparator. The comparator compares the operation result with the expected result, and provides a comparison result for the test result storage unit.

Abstract: A high-performance data cache system and method is provided for facilitating operation of a processor core. The method includes examining instructions to generate stride length of base register value corresponding to every data access instruction; based on the stride length of base register value, calculating possible a data access address of the data access instruction to be executed next time; based on the calculated the possible data access address of the data access instruction to be executed next time, prefetching data and filling the data to cache memory before the processor core accesses the data. The processor core may access directly the needed data from the cache memory almost every time, thus getting very high cache hit rate.

Abstract: A method for assisting operations of a processor core coupled to a first memory and a second memory includes: examining instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information of the instructions, and creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling one or more instructions from the first memory to the second memory based on one or more tracks from the plurality of tracks before the processor core starts executing the instructions, such that the processor core fetches the instructions from the second memory for execution. Filling the instructions further includes pre-fetching from the first memory to the second memory instruction segments containing the instructions corresponding to at least two levels of branch target instructions based on the one or more tracks.

Abstract: A method for facilitating operation of a processor core is provided. The method includes: examining instructions being filled from a second instruction memory to a third instruction memory, extracting instruction information containing at least branch information and generating a stride length of base register corresponding to every data access instruction; creating a plurality of tracks based on the extracted instruction; filling at least one or more instructions that are likely to be executed by the processor core based on one or more tracks from the plurality of tracks from a first instruction memory to the second instruction memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second instruction memory to the third instruction memory; calculating possible data access address of the data access instruction to be executed next time based on the stride length of the base register.

Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.

Abstract: An information processing system is provided. The information processing system includes a processor used to obtain information, a memory used to store the information and output an information block based on a received address; and a scanner used to generate an address based on the current information block and to provide the address to the memory, where the current information block is the information block currently outputted from the memory. Thus, the speed for obtaining the information block by the processor (information block requested device) is further improved, and the execution speed of the processor and the information processing system is improved.