Abstract: An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

Abstract: Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.

Abstract: An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

Abstract: A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

Abstract: A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

Abstract: A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.

Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.

Abstract: The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Abstract: A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit. The calibration circuit includes a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein. A frequency of the DCO is set by the calibration control signal. The delay line includes a second plurality of delay stages that are replicas of the first plurality of delay stages. The calibration circuit may include a current steering digital-to-analog converter (CSDAC), which is responsive to a digital calibration code, and a current-to-voltage converter, which is responsive to at least one current signal generated by the CSDAC. The DCO and other portions of the calibration circuit are disabled into a low power state upon completion of a calibration operation, which may commence upon start-up.

Abstract: The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Abstract: The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Abstract: The present invention discloses a liquid crystal display (LCD) panel and method for forming the same. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is very proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD of the present invention is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Abstract: An LCD panel and method for forming the same are proposed. In the LCD panel, the TFT includes a source and a drain formed by a transparent conducting layer, and a gate formed by a metal layer. The source is electrically connected with a data line through a via hole over the data line. The source connects to the drain via an active layer. Whatever the number of data lines are, each pixel corresponds to an associated via hole, so the number of via holes does not increase, and not reduce the aperture ratio. Therefore, the present invention is proper to a design using more data lines and working in a high frequency. Moreover, the matrix circuitry of LCD is well applied in a display which not only increases a density of data lines to raise the frame rate, but also maintains the aperture ratio and brightness.

Abstract: The present invention provides methods for manufacturing a passivation layer and a thin film transistor (TFT) array substrate. The method for manufacturing the passivation layer comprises the following steps: placing a substrate in a vacuum process chamber; providing an ammonia gas and a nitrogen gas into the vacuum process chamber; forming plasma and evaporating water vapor; and forming the passivation layer on the substrate. The method for manufacturing the passivation layer can be applicable to the method for manufacturing the TFT array substrate. The present invention can enhance the quality of the passivation layer.

Abstract: A liquid crystal display (LCD) device is disclosed. The LCD device comprises a plurality of pixel units arranged in the form of a matrix. Each of the pixel units comprises: a scan line; a data line; a first storage capacitor; a liquid crystal capacitor; and a first TFT, having a source electrically connected to the data line, a gate electrically connected to the scan line, and a drain electrically connected to the first storage capacitor. Each of the pixel units further comprises a second TFT, having a gate, a source electrically connected to the drain of the first TFT, and a drain electrically connected to the liquid crystal capacitor. The gates of the second TFTs are electrically connected with each other to control the second TFTs to be turned on simultaneously so as to tilt the liquid crystal molecules. Because this shortens the time to wait for scanning of the gates is shortened and increases the time duration in which the backlight can emit light, the number of LEDs can be reduced to lower the cost.

Abstract: Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.

Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.

Abstract: A liquid crystal display (LCD) drive circuit and a driving method thereof are disclosed. The driving method comprises: a. dividing scan lines into a plurality of groups each comprising a plurality of scan lines; b. during displaying of a current image frame, using a scan driver to scan each group of scan lines sequentially, c. during displaying of a next image frame, using the scan driver to scan each group of scan lines sequentially; and d. if each scan line in the group has been scanned once simultaneously with an adjacent scan line within a predetermined time interval, then the step b is executed; otherwise, the step c is executed. The LCD drive circuit and the driving method thereof according to the present disclosure can increase an average charging time of pixel units without compromising the accuracy of image frames.

Abstract: Disclosed are a 3D image system and 3D glasses. The 3D image system includes a liquid crystal display monitor and the 3D glasses. The liquid crystal display monitor includes a backlight module and a ½? wave plate. The ½? wave plate converts lights from by the backlight module into linear polarized lights. The 3D glasses includes a first ¼? wave plate for receiving and converting the linear polarized lights from the ½? wave plate into circular polarized lights, a second ¼? wave plate for converting the circular polarized lights from the first ¼? wave plate into linear polarized lights, and a second ¼? wave plate for filtering the linear polarized lights from the second ¼? wave plate and transmitting the filtered lights to left and right eyes correspondingly. The present invention saves the cost and decreases the maintaining expense.

Abstract: The present invention discloses a TFT, an LCD panel and method for manufacturing the same. In the LCD panel, a transparent conducting layer forms a first electrode of a TFT and a second electrode of a TFT directly, and the transparent conducting layer also serves as a connecting line between a TFT and a data line and between a TFT and an LC capacitor. So it is not necessary to form a via hole over the TFT to link the TFT and the transparent conducting layer. In this way, an area of a pixel electrode can be further extended, and the aperture rate of an LCD panel can be also increased, raising a transmittance of light from light sources passing through the pixel electrode In this way, not only a design in pixels becomes more flexible but also the aperture rate of an LCD panel becomes higher.