Patents by Inventor Chenguang Yin

Chenguang Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735554
    Abstract: The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: August 22, 2023
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Chenguang Yin, Yenheng Chen
  • Publication number: 20220052011
    Abstract: The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.
    Type: Application
    Filed: March 12, 2021
    Publication date: February 17, 2022
    Inventors: Chenguang YIN, Yenheng Chen
  • Patent number: 11032287
    Abstract: A method and system for generating permissions policies and permission boundary policies are described. The system receives a first request from a central administrator to create a delegated administrator, the first request specifying with one or more access permissions. The system generates a permission boundary policy that specifies the one or more access permissions and a first permissions policy that grants permissions to the delegated administrator to at least one of create an IAM principal with the permission boundary policy or attach a second permissions policy to the IAM principal. An effective permission given to the IAM principal is an intersection of access permissions specified in the first permissions policy and the one or more access permissions in the permission boundary policy. The system attaches the first permissions policy and the permission boundary policy to the delegated administrator.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 8, 2021
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Mingkun Wang, Jasmeet Chhabra, Hang Li, Chenguang Yin, Dan Popick, Alazel Acheson, Apurv Awasthi, Brigid Ann Johnson, Conor P. Cahill