Patents by Inventor Cheol-Ho Cho

Cheol-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8796766
    Abstract: A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Cheol Ho Cho
  • Patent number: 8692327
    Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Choul Joo Ko, Cheol Ho Cho
  • Patent number: 8637923
    Abstract: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: January 28, 2014
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Cheol-Ho Cho
  • Publication number: 20130093014
    Abstract: A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor.
    Type: Application
    Filed: April 3, 2012
    Publication date: April 18, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Cheol Ho CHO
  • Publication number: 20130093016
    Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.
    Type: Application
    Filed: May 21, 2012
    Publication date: April 18, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventors: Choul Joo KO, Cheol Ho CHO
  • Publication number: 20130082327
    Abstract: A semiconductor device including a first conductive epitaxial layer, a second conductive type first well provided in the first conductive epitaxial layer, a first conductive body provided in the first conductive epitaxial layer, a second conductive type drain extension region provided in the first conductive epitaxial layer and interposed between the first conductive body and the second conductive type first well, a second conductive type second well provided in the second conductive type first well, and a gate provided in the first conductive epitaxial layer.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Inventors: Cheol Ho CHO, Choul Joo Ko
  • Publication number: 20120187484
    Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a first buried layer having a second conduction type formed in an epitaxial layer having a first conduction type, a first high-voltage well having the second conduction type formed above one region of the first buried layer, a first drain diffusion region having the first conduction type formed above another region of the first buried layer, a second drain diffusion region having the second conduction type formed in a partial region of the first drain diffusion region, the second drain diffusion region including a gate pattern and a drain region, and a first body having the first conduction type including a source region and having a surface in contact with the second drain diffusion region.
    Type: Application
    Filed: August 24, 2011
    Publication date: July 26, 2012
    Inventors: Cheol-Ho CHO, Choul-Joo Ko
  • Patent number: 8183632
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: May 22, 2012
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Cheol Ho Cho
  • Patent number: 8105939
    Abstract: A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a top surface of the first dielectric layer; a plurality of contact plugs spaced apart by a predetermined distance in an active region of the substrate, passing through the first and second dielectric layers; and a bridge metal line formed in the second dielectric layers, inter-connecting the contact plugs in a horizontal direction. The bridge metal line formed to inter-connect the contact plugs allows for more current to flow in the presently disclosed LDMOS transistor than in a conventional LDMOS transistor of identical size.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: January 31, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Cheol Ho Cho
  • Publication number: 20100258865
    Abstract: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 14, 2010
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Cheol-Ho CHO
  • Patent number: 7767530
    Abstract: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: August 3, 2010
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Cheol-Ho Cho
  • Publication number: 20100148258
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 17, 2010
    Inventor: CHEOL HO CHO
  • Publication number: 20100123196
    Abstract: A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a top surface of the first dielectric layer; a plurality of contact plugs spaced apart by a predetermined distance in an active region of the substrate, passing through the first and second dielectric layers; and a bridge metal line formed in the second dielectric layers, inter-connecting the contact plugs in a horizontal direction. The bridge metal line formed to inter-connect the contact plugs allows for more current to flow in the presently disclosed LDMOS transistor than in a conventional LDMOS transistor of identical size.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 20, 2010
    Inventor: Cheol Ho CHO
  • Publication number: 20080150015
    Abstract: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.
    Type: Application
    Filed: September 18, 2007
    Publication date: June 26, 2008
    Inventor: Cheol-Ho Cho