Patents by Inventor Cheol Ho Joh
Cheol Ho Joh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170162516Abstract: A method of fabricating a semiconductor package is provided. The method includes providing a package substrate strip including chip mounting regions, bridge regions connecting the chip mounting regions to each other, and through slits disposed between the chip mounting regions. A side shielding part including a lower portion filling the through slits and an upper portion upwardly extending from the lower side shielding part to protrude from the package substrate strip is formed. Semiconductor chips are mounted on the chip mounting regions. Mold patterns are formed on the package substrate strip to cover the semiconductor chips and to expose a top surface of the side shielding part. A top shielding part is formed on the mold patterns to contact the side shielding part.Type: ApplicationFiled: May 20, 2016Publication date: June 8, 2017Inventor: Cheol Ho JOH
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Patent number: 9490187Abstract: The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.Type: GrantFiled: August 15, 2014Date of Patent: November 8, 2016Assignee: SK HYNIX INC.Inventor: Cheol Ho Joh
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Patent number: 9305912Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: June 9, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Hee Min Shin, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Kyu Won Lee
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Patent number: 9165899Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.Type: GrantFiled: November 19, 2013Date of Patent: October 20, 2015Assignee: SK Hynix Inc.Inventor: Cheol Ho Joh
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Publication number: 20150279758Abstract: The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window; a first semiconductor chip disposed within the window and having a plurality of first bonding pads arranged over edges of an upper surface; a plurality of first connection members electrically coupling the first bonding pads with the first bonding fingers; a second semiconductor chip disposed over the first semiconductor chip and the first surface of the substrate and a plurality of second bonding pads in the edges of the lower surface; a plurality of second connection members electrically coupling the second bonding pads with the second bonding fingers of the substrate adjacent to the second bonding pads; and an encapsulation member formed over the first surface of the substrate to cover side surfaces of the second semiconductor chip.Type: ApplicationFiled: August 15, 2014Publication date: October 1, 2015Inventor: Cheol Ho JOH
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Publication number: 20150270252Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: June 9, 2015Publication date: September 24, 2015Inventors: Hee Min SHIN, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Kyu Won LEE
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Patent number: 9093441Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.Type: GrantFiled: March 18, 2013Date of Patent: July 28, 2015Assignee: SK Hynix Inc.Inventors: Ji Eun Kim, Cheol Ho Joh, Hee Min Shin, Kyu Won Lee, Chong Ho Cho
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Patent number: 9082634Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: GrantFiled: December 29, 2010Date of Patent: July 14, 2015Assignee: SK Hynix Inc.Inventors: Hee-Min Shin, Cheol-Ho Joh, Eun-Hye Do, Ji-Eun Kim, Kyu-Won Lee
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Patent number: 8951810Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.Type: GrantFiled: December 18, 2012Date of Patent: February 10, 2015Assignee: SK hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
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Publication number: 20150008580Abstract: The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls.Type: ApplicationFiled: November 19, 2013Publication date: January 8, 2015Applicant: SK hynix Inc.Inventor: Cheol Ho JOH
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Patent number: 8822271Abstract: There are proposed a method and apparatus for manufacturing a chip package in which bonding wires are coupled with contact pads in which an overhang holder holds and fixes portions of a surface adjacent to portions where the contact pads are located.Type: GrantFiled: March 18, 2013Date of Patent: September 2, 2014Assignee: SK Hynix Inc.Inventor: Cheol Ho Joh
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Publication number: 20140175638Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.Type: ApplicationFiled: March 18, 2013Publication date: June 26, 2014Applicant: SK HYNIX INC.Inventors: Ji Eun KIM, Cheol Ho JOH, Hee Min SHIN, Kyu Won LEE, Chong Ho CHO
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Publication number: 20140170812Abstract: There are proposed a method and apparatus for manufacturing a chip package in which bonding wires are coupled with contact pads in which an overhang holder holds and fixes portions of a surface adjacent to portions where the contact pads are located.Type: ApplicationFiled: March 18, 2013Publication date: June 19, 2014Applicant: SK HYNIX INC.Inventor: Cheol Ho JOH
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Publication number: 20140057369Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: Kyu Won LEE, Cheol-Ho JOH, Ji Eun KIM, Hee-Min SHIN, Chong Ho CHO
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Patent number: 8564141Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: GrantFiled: March 2, 2011Date of Patent: October 22, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20130256887Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Applicant: SK hynix Inc.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN
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Patent number: 8476751Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: GrantFiled: April 28, 2011Date of Patent: July 2, 2013Assignee: SK Hynix Inc.Inventors: Kyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
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Publication number: 20120018879Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.Type: ApplicationFiled: December 29, 2010Publication date: January 26, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hee-Min SHIN, Cheol-Ho JOH, Eun-Hye DO, Ji-Eun KIM, Kyu-Won LEE
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Publication number: 20110272798Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.Type: ApplicationFiled: March 2, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun Hye DO, Ji Eun KIM, Hee Min SHIN
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Publication number: 20110272820Abstract: A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.Type: ApplicationFiled: April 28, 2011Publication date: November 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyu Won LEE, Cheol Ho JOH, Eun-Hye DO, Ji Eun KIM, Hee Min SHIN