Patents by Inventor Cheol-Joon Yoo

Cheol-Joon Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110169195
    Abstract: Provided are a molding apparatus and a molding method. The molding apparatus a mold including a cavity and a runner. The molding apparatus may further include a pot connected to the runner of the mold, wherein a fluid resin is contained in the pot The molding apparatus may further include a compression gas injection unit configured to inject a compression gas into the pot such that the fluid resin contained in the pot is transferred to the cavity and the runner.
    Type: Application
    Filed: December 8, 2010
    Publication date: July 14, 2011
    Inventor: Cheol-joon YOO
  • Patent number: 7939924
    Abstract: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Publication number: 20100013079
    Abstract: A package substrate may include an insulating substrate, a circuit pattern and a mold gate pattern. The insulating pattern may have a mold gate region through which a molding member may pass. The circuit pattern may be formed on the insulating substrate. The mold gate pattern may be formed on the mold gate region of the insulating substrate. The mold gate pattern may include a polymer having relatively strong adhesion strength with respect to the insulating substrate and relatively weak adhesion strength with respect to the molding member. Thus, costs of the package substrate and the semiconductor package may be decreased.
    Type: Application
    Filed: July 16, 2009
    Publication date: January 21, 2010
    Applicant: Samsung Electronics Co., Ltd
    Inventors: In-Sik Cho, Yong-Kwan Lee, Cheol-Joon Yoo
  • Publication number: 20090166061
    Abstract: A PCB strip, a PCB strip assembly device, and methods of fabricating a PCB strip and using a PCB strip assembly device are provided. According to example embodiments, a PCB strip may include a PCB main body including a working area based on a process execution unit, wherein the working area may be divided into a first working area and a second working area and a plurality of units on the working area arrayed with a given interval in at least a width direction of the PCB main body, wherein the plurality of units may be arrayed on the first working area and the second working area and units on the first working area may be symmetric to units on the second working area with respect to a point of symmetry at a center of width of the working area.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 2, 2009
    Inventors: Cheol-Joon Yoo, Tae-Sung Park
  • Patent number: 7485959
    Abstract: A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Joon Yoo, Jin-Ho Kim, Hee-Jin Park, Tae-Sung Yoon, Chan-Suk Lee
  • Publication number: 20080308935
    Abstract: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.
    Type: Application
    Filed: June 18, 2008
    Publication date: December 18, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lyong KIM, Eun-Chul AHN, Jong-Ho LEE, Cheul-Joong YOUN, Min-Ho O, Tae-Sung YOON, Cheol-Joon YOO
  • Patent number: 7465142
    Abstract: A method and apparatus for picking up a semiconductor chip, a method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape are provided. Air may be blown through air holes in a dicing tape to at least partially separate the semiconductor chip from the dicing tape and/or create a space between the semiconductor chip to weaken the adhesion of the dicing tape to the semiconductor chip. The semiconductor chip may then be picked up by a removal member and completely removed from the dicing tape. Semiconductor chips that are not to be removed may be vacuum-suctioned to the dicing tape. UV radiation or heat may be applied to weaken the adhesion of the dicing tape. The semiconductor chip may be detected by an optical detector. Removing the semiconductor chips by air reduces stress and damage to the semiconductor chips.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Publication number: 20080296780
    Abstract: Wires included in integrated circuit devices can have separate insulating structures formed thereon. The separate insulating structures on the wires can surround respective cross sectional portions of the wires, which can function as “stand-offs” to prevent immediately neighboring wires (or other neighboring components) from shorting together to thereby allow a reduction in defects associated with devices having reduced pitch between the wires (or other components).
    Type: Application
    Filed: April 17, 2008
    Publication date: December 4, 2008
    Inventor: Cheol-joon Yoo
  • Publication number: 20080111284
    Abstract: In a method of molding a substrate, a molding structure including a release film and flat plate-shaped epoxy molding compound (EMC) is placed on an upper face of a lower die. The substrate is held by a lower face of an upper die facing the lower die. The molding structure and the substrate are compressed using the lower die and the upper die to form a preliminarily molded substrate. The lower die is then downwardly moved from the upper die to form a molded substrate.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 15, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Joon Yoo, Tae-Sung Yoon
  • Publication number: 20080042253
    Abstract: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.
    Type: Application
    Filed: October 23, 2007
    Publication date: February 21, 2008
    Inventor: Cheol-Joon Yoo
  • Patent number: 7298033
    Abstract: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Patent number: 7284941
    Abstract: A method and apparatus for picking up a semiconductor chip, a method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape are provided. Air may be blown through air holes in a dicing tape to at least partially separate the semiconductor chip from the dicing tape and/or create a space between the semiconductor chip to weaken the adhesion of the dicing tape to the semiconductor chip. The semiconductor chip may then be picked up by a removal member and completely removed from the dicing tape. Semiconductor chips that are not to be removed may be vacuum-suctioned to the dicing tape. UV radiation or heat may be applied to weaken the adhesion of the dicing tape. The semiconductor chip may be detected by an optical detector. Removing the semiconductor chips by air reduces stress and damage to the semiconductor chips.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: October 23, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Patent number: 7279360
    Abstract: Embodiments of the invention provide a semiconductor-chip mounting body, a semiconductor device including the mounting body, and a method of packaging the semiconductor device. According to some embodiments, when a semiconductor chip is mounted on the mounting body as a flip-chip type, an encapsulation process using an encapsulation resin is not required. In some embodiments, the mounting body includes a substrate formed of a polyimide film, a conductive pattern formed of copper, a protection layer pattern formed of PSR, and an adhesive pattern formed on the protection layer pattern. The adhesive pattern can be formed of an insulating material. A plurality of holes, into which a plurality of bumps formed on the semiconductor chip are inserted to be connected to the conductive pattern, are formed in the protection layer pattern and the adhesive pattern.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Publication number: 20070049002
    Abstract: Embodiments of the invention provide a semiconductor-chip mounting body, a semiconductor device including the mounting body, and a method of packaging the semiconductor device. According to some embodiments, when a semiconductor chip is mounted on the mounting body as a flip-chip type, an encapsulation process using an encapsulation resin is not required. In some embodiments, the mounting body includes a substrate formed of a polyimide film, a conductive pattern formed of copper, a protection layer pattern formed of PSR, and an adhesive pattern formed on the protection layer pattern. The adhesive pattern can be formed of an insulating material. A plurality of holes, into which a plurality of bumps formed on the semiconductor chip are inserted to be connected to the conductive pattern, are formed in the protection layer pattern and the adhesive pattern.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 1, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Cheol-Joon Yoo
  • Patent number: 7170158
    Abstract: A multi-chip package comprises a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee Kook Choi, Cheol Joon Yoo
  • Patent number: 7129118
    Abstract: A method of utilizing a removable protective tape to protect the active surfaces of semiconductor wafer and the individual semiconductor chips during semiconductor packaging processes is provided along with several configurations of apparatuses that may be used in such a method for removing protective tape portions from individual semiconductor chips during the assembly process.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: October 31, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Joon Yoo, Ki-Kwon Jeong
  • Patent number: 7129585
    Abstract: Embodiments of the invention provide a semiconductor-chip mounting body, a semiconductor device including the mounting body, and a method of packaging the semiconductor device. According to some embodiments, when a semiconductor chip is mounted on the mounting body as a flip-chip type, an encapsulation process using an encapsulation resin is not required. In some embodiments, the mounting body includes a substrate formed of a polyimide film, a conductive pattern formed of copper, a protection layer pattern formed of PSR, and an adhesive pattern formed on the protection layer pattern. The adhesive pattern can be formed of an insulating material. A plurality of holes, into which a plurality of bumps formed on the semiconductor chip are inserted to be connected to the conductive pattern, are formed in the protection layer pattern and the adhesive pattern.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: October 31, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-Joon Yoo
  • Publication number: 20060157848
    Abstract: In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 20, 2006
    Inventors: Cheol-Joon Yoo, Jin-Ho Kim, Hee-Jin Park, Tae-Sung Yoon, Chan-Suk Lee
  • Publication number: 20050280503
    Abstract: A semiconductor wafer, comprising a radio frequency identification (RFID) chip on one side of the semiconductor wafer, on which a pattern has been formed, wherein information on the wafer is input to and/or output from the RFID chip using radio frequency communication.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 22, 2005
    Inventors: Sang-Woo Lee, Cheol-Joon Yoo, Dong-Bin Kim
  • Publication number: 20050269715
    Abstract: An apparatus, method and mold for manufacturing a semiconductor package are provided. The semiconductor package may include at least a semiconductor chip positioned on a substrate, a bonding wire for electrically connecting the semiconductor chip to the substrate, an encapsulant for enclosing the semiconductor chip and sides of the substrate, and a conductor connector attached to a lower surface of the substrate.
    Type: Application
    Filed: January 6, 2005
    Publication date: December 8, 2005
    Inventor: Cheol-Joon Yoo