Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Abstract: Disclosed herein is a device for producing a polymer dispersion solution of core-shell structured silicon nanoparticles. The device includes: a canister for storing silicon nanoparticles; a quantitative feeder for receiving the silicon nanoparticles released from the canister and for quantitatively feeding the same; a mixing tank for mixing block copolymer constituting a shell, and a dispersion solvent, and the silicon nanoparticles fed through the quantitative feeder to form core-shell structured silicon nanoparticles; an ultrasonic disperser for receiving the core-shell structured silicon nanoparticles released from the mixing tank and a dispersion solvent and for dispersing the particles with ultrasonic waves; and a dispersion solvent tank for feeding a dispersion solvent into the mixing tank and the ultrasonic disperser.

Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.

Abstract: In a method of forming a wiring structure, a carbon-containing layer may be formed on a substrate. A conductive layer may be formed on the carbon-containing layer, and the conductive layer may be formed to include a metal. The conductive layer and an upper portion of the carbon-containing layer may be etched to form a wiring and a carbon-containing layer pattern, respectively.

Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.

Abstract: A method of manufacturing a pattern structure, the method includes sequentially forming a mold layer and a mask layer on a substrate, patterning the mask layer to form a mask having a plurality of first and second holes located at vertices of hexagons that form a honeycomb structure, forming filling layer patterns in the first and second holes, removing the mask, forming a spacer on sidewalls of the filling layer patterns and the spacer has a plurality of third holes at centers of the hexagons, removing the filling layer patterns to form an etching mask including the spacer, and etching the mold layer using the etching mask to form the pattern structure having a plurality of openings located at the vertices and the centers of the hexagons.

Abstract: In one embodiment, a preliminary insulation layer is formed over a cell region and a peripheral circuit region of a semiconductor substrate. The preliminary insulation layer covers a capacitor formed over the cell region. The preliminary insulation layer over the cell region has a first height higher than a second height of the preliminary insulation layer over the peripheral circuit region. A preliminary node separate polymer layer is formed over the preliminary insulation layer. A portion of the preliminary node separate polymer layer is uniformly removed by a developing process to form a node separate polymer layer exposing the preliminary insulation layer over the cell region. A portion of the preliminary insulation layer over the cell region is removed to form an insulation layer.