Abstract: A process for the manufacture of semiconductor integrated circuits is described in which the defect density due to conductive particle debris formed at the edge of the wafer is reduced by burying the edges of the metal layers in a tapered step configuration, so that the maximum steps in the interlevel and final dielectric layers are essentially the same as the thickness of the metal layers.

Abstract: A method is provided for performing in-line process checks in an integrated circuit fabrication process. The process checks are performed on actual product wafers, rather than control wafers. According to the method, production lots of product wafers are subjected to in-line testing. Selected wafers representing each chamber of the fabrication apparatus are tested for defects. Using the actual product wafers allows the detection of the quantity, size, type, composition, and even the cause of the defects. When defects are found, the fabrication process and apparatus are adjusted to avoid producing additional lots with undesirable defects.