Abstract: A cell for use in a packet switching network. The cell comprises an input for receiving a packet including a destination address and first and second outputs. The cell includes a selection circuit for connecting the input with the first output or the second output depending on whether a specific bit occupying a predetermined position in the packet address is a logic "1" or a logic "0". Illustratively, the specific bit is the first bit after a start bit of the packer and each of the cells includes means for rotating the specific bit to the end of the address. This is especially useful for implementing a banyan network wherein the k.sup.th column of cells the routing decision is based on the k.sup.th most significant bit of the address, as the address bit rotation mechanism can be used to ensure that the first bit after the start bit of a packet is the k.sup.th most significant address bit.

Abstract: A Batcher-banyan network which may be implemented using only two different IC chip designs is disclosed. The chips comprising the Batcher banyan network are arranged in adjacent horizontal and vertical stacks to minimize the lengths of electrical conductors connecting the chips.

Abstract: A mechanism is disclosed for resolving conflicts between input ports of a Batcher-Banyan Packet switching network that wish to transmit data packets to the same output port during a particular packet switch cycle. The input ports of the Batcher-Banyon network are connected in a serial ring. Bit positions on the ring represent output ports. Each input port having a data packet to transmit to a particular output port may reserve that output port before the start of the next Batcher-Banyan packet switch cycle by writing a "1" in the ring bit position corresponding to the output port to which the data packet is addressed. If the particular output port has already been reserved by another input port, the data packet is buffered.