Patents by Inventor Chester Pawlowski

Chester Pawlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176739
    Abstract: In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: STRATUS TECHNOLOGIES IRELAND LTD.
    Inventors: Andrew Alden, Chester Pawlowski, Christopher Cotton, John Chaves
  • Patent number: 6085263
    Abstract: An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: July 4, 2000
    Assignee: Compaq Computer Corp.
    Inventors: Madhumitra Sharma, Chester Pawlowski, Kourosh Gharachorloo, Stephen R. Van Doren, Simon C. Steely, Jr.
  • Patent number: 5652837
    Abstract: The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: July 29, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Nicholas Allen Warchol, Chester Pawlowski