Patents by Inventor Chester Szwejkowski

Chester Szwejkowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5338398
    Abstract: A process for etching tungsten silicide on a semiconductor wafer in a vacuum etch chamber in the presence of a plasma is described using chlorine (Cl.sub.2) and oxygen-bearing etchant gases in a ratio of not more that 20 volume % oxygen-bearing etchant gas, and preferably from about 6 to about 10 volume % oxygen-bearing etchant gas. The process is also capable of etching polysilicon and exhibits a high selectivity for both photoresist and oxide.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: August 16, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Chester A. Szwejkowski, Robert Lum, Thierry Fried
  • Patent number: 5296093
    Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous ammonium-containing base/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: March 22, 1994
    Assignees: Applied Materials, Inc., Seiko Epson Corp.
    Inventors: Chester Szwejkowski, Ian S. Latchford, Isamu Namose, Kazumi Tsuchida
  • Patent number: 5228950
    Abstract: A process is disclosed for the removal of residual oxide and/or silicon materials from a semiconductor wafer such as silicon-rich oxide residues or polysilicon stringers from the sidewalls of lines or steps formed over semiconductor wafers during the construction of integrated circuit structures without removing the wafer from the vacuum apparatus used in forming the lines on the wafer using a high pressure magnetically enhanced plasma etch using an NF.sub.3 -containing gas containing at least about 40 volume % NF.sub.3 as the etchant gas.
    Type: Grant
    Filed: December 4, 1990
    Date of Patent: July 20, 1993
    Assignee: Applied Materials, Inc.
    Inventors: Jennifer M. Webb, Chester A. Szwejkowski, Zahra H. Amini
  • Patent number: 5147499
    Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous hydroxide/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: September 15, 1992
    Assignee: Applied Materials, Inc.
    Inventors: Chester Szwejkowski, Ian S. Latchford, Isamu Namose, Kazumi Tsuchida