Patents by Inventor Chetan Agrawal

Chetan Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240169411
    Abstract: A computerized system and method for dynamically generating modified user interface is disclosed. The method comprises receiving a search request, providing a list of at least one product in response to the search request, receiving a selection of a first product from the user device, providing the first product to the user device for display on the user interface, determining signals of the first product and their weights, calculating a score for each of the second products based on signals of the first product, ranking the second products by the score, and in response to receiving a request to redisplay the list of product, providing, to the user device for display together with the list of product, at least one second product based on the ranking.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Inventors: Nishant AGRAWAL, Chetan RAO, Ashutosh PENDSE, Yiwei SUN, Taeoh KIM, Dongcheng WANG
  • Patent number: 11966476
    Abstract: In an embodiment, a method for deep application discovery and forensics of a reference system includes a computing device, such as an orchestrator, receiving and/or obtaining from an inspection layer executing on the reference system, during runtime of the reference system, architecture and configuration information describing the reference system. Also, the computing device generates, during runtime of the reference system, dependency matrices describing relationships between components of the reference system which allow for generation, during runtime of the reference system, at least one threat model describing vulnerabilities of the reference system based on the dependency matrices. The inspection layer identifies the applications and databases accessed by the applications.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 23, 2024
    Assignee: Avocado Systems, Inc.
    Inventors: Keshav Kamble, Chetan Gopal, Girish Joag, Annu Agrawal
  • Patent number: 11507303
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Publication number: 20220342585
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Inventors: Amit SHARMA, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Patent number: 11437104
    Abstract: A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Publication number: 20220076753
    Abstract: A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.
    Type: Application
    Filed: February 22, 2021
    Publication date: March 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Patent number: 10635326
    Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Chetan Agrawal, Dinesh Agarwal, Vijay Sivasankaran
  • Publication number: 20180129428
    Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.
    Type: Application
    Filed: December 20, 2017
    Publication date: May 10, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Chetan Agrawal, Dinesh Agarwal, Vijay Sivasankaran
  • Patent number: 9875039
    Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Chetan Agrawal, Dinesh Agarwal, Vijay Sivasankaran
  • Patent number: 9542286
    Abstract: A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary block when the secondary block is picked as the source block for garbage collection.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 10, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Kaushik Kumar Bar, Chetan Agrawal, Dinesh Agarwal, Vimal Kumar Jain
  • Publication number: 20160092325
    Abstract: A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary block when the secondary block is picked as the source block for garbage collection.
    Type: Application
    Filed: April 30, 2015
    Publication date: March 31, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Kaushik Kumar Bar, Chetan Agrawal, Dinesh Agarwal, Vimal Kumar Jain
  • Publication number: 20160092122
    Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.
    Type: Application
    Filed: April 30, 2015
    Publication date: March 31, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Chetan Agrawal, Dinesh Agarwal, Vijay Sivasankaran