Abstract: A video request manager comprises a first state machine. The first state machine commands a memory controller to fetch reference pixels for a first portion of a picture. The second state machine commands a memory controller to write a second portion of the picture.

Abstract: Presented herein are system(s), method(s), and apparatus for converting unsigned fixed length codes to signed fixed length codes. In one embodiment, there is presented a circuit for converting an unsigned code to a signed code. The circuit comprises a multiplexer. The multiplexer comprises a first input, a second input, and an output. The first input receives a first value, the first value being the right shifted unsigned code plus one. The second input receives a second value, the second value being an inverse of a right shifted unsigned code plus one. The output outputs a selected one of the first value received by the first input or the second value received by the second input. The multiplexer selects the selected one of the first value or the second value based on a least significant bit of the unsigned code.

Abstract: Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit pointer, a first logic circuit, and a comparator. The multiplexer provides one or more bits from the one or more data words. The bit pointer points to the bits following the provided one or more bits in the one or more data words. The first logic circuit examines at least portions of the data words for an end of data structure code, the at least portions comprising the one or more bits, and provides an indicator indicating the position of the end of data structure code. The comparator compares the indicator to where the bit pointer points.

Abstract: Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.

Abstract: Presented herein are system(s), method(s), and apparatus for decoding exponential Golomb codes. In one embodiment, there is presented a system for decoding codes having lengths (L) and information bits. The system comprises a circuit and a multiplexer. The circuit provides the information bits of the codes. The multiplexer provides values for the codes, the values for the codes being a function of 2trunc(L/2).

Abstract: Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.

Abstract: Presented herein are system(s), method(s), and apparatus for decoding exponential Golomb codes. In one embodiment, there is presented a system for decoding codes having lengths (L) and information bits. The system comprises a circuit and a multiplexer. The circuit provides the information bits of the codes. The multiplexer provides values for the codes, the values for the codes being a function of 2trunc(L/2).

Abstract: Presented herein are video system(s), method(s), and apparatus for extracting slice groups from data words. According to one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a barrel shifter, another multiplexer, and a bit pointer. The multiplexer divides the one or more data words into a plurality of smaller data words. The barrel shifter shiftings the smaller data words. The other multiplexer provides one or more bits from one or more of the smaller data words. The bit pointer points to a bit following the provided one or more bits in the one or more of the smaller data words.

Abstract: Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit pointer, a first logic circuit, and a comparator. The multiplexer provides one or more bits from the one or more data words. The bit pointer points to the bits following the provided one or more bits in the one or more data words. The first logic circuit examines at least portions of the data words for an end of data structure code, the at least portions comprising the one or more bits, and provides an indicator indicating the position of the end of data structure code. The comparator compares the indicator to where the bit pointer points.

Abstract: Presented herein are system(s), method(s), and apparatus for converting unsigned fixed length codes to signed fixed length codes. In one embodiment, there is presented a circuit for converting an unsigned code to a signed code. The circuit comprises a multiplexer. The multiplexer comprises a first input, a second input, and an output. The first input receives a first value, the first value being the right shifted unsigned code plus one. The second input receives a second value, the second value being an inverse of a right shifted unsigned code plus one. The output outputs a selected one of the first value received by the first input or the second value received by the second input. The multiplexer selects the selected one of the first value or the second value based on a least significant bit of the unsigned code.

Abstract: Presented herein is a video decoder for supporting both single and four motion vector macroblocks. In one embodiment, the video decoder comprises a processor, a motion vector address computer, a video request manager, and a pixel reconstructor. The processor decodes a set of parameters. The set of parameters comprises motion vectors indicating reference pixels associated with the macroblock. The motion vector address computer calculates addresses associated with motion vectors. The video request manager fetches a block of reference pixels at the addresses calculated by the motion vector address computer. The pixel reconstructor reconstructs pixels from the macroblocks. The pixel reconstructor is operable to reconstruct pixels from macroblocks encoded in accordance with a plurality of standards.

Abstract: A video request manager comprises a first state machine. The first state machine commands a memory controller to fetch reference pixels for a first portion of a picture. The second state machine commands a memory controller to write a second portion of the picture.

Abstract: Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

Abstract: Presented herein is a direct memory access engine for providing data words in reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order. A set of multiplexers reverses the bit positions of the words in the local buffer.

Abstract: A system, method, and apparatus for reducing memory and processing requirements in a decoder system are presented herein. The memory and processing requirements are reduced by generating virtual pixels on the fly. Generating the virtual pixels on the fly, as opposed to storing the virtual pixels reduces the memory requirements of the frame buffer. Additionally, generation on the fly also reduces the fetch instructions required to retrieve the virtual pixels from the frame buffer.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.