Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.

Abstract: In one or more embodiments, a fan circuit may be configured with an input of a first amplifier coupled to a revolution indicator associated with a fan; an output of the first amplifier coupled to an input of a second amplifier; and a power supply input of the second amplifier coupled to a first contact of a first connector. In one or more embodiments, the first contact of the first connector may be coupled to a first contact of a second connector to drive a resistive load coupled to the first contact of the second connector; a second contact of the first connector may be coupled to a second contact of the second connector to provide a reference voltage to the second amplifier; and the second amplifier may provide amplified signals to the first contact of the first connector based at least on signals received from the revolution indicator.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.

Abstract: A method for reducing the scrap rate of fuse structures after laser repairing is provided. The method includes providing a semiconductor wafer comprising integrated circuits, performing a yield test on the semiconductor wafer to determine defective circuits, predetermining a wavelength limit, and keeping the semiconductor wafer away from lights having wavelengths lower than the wavelength limit. The defects on the semiconductors wafer are repaired by burning laser fuses. For copper-based fuse structures, the wavelength limit is about 550 nm.