Patents by Inventor Chi-Chih Chu
Chi-Chih Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140312496Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: ApplicationFiled: April 30, 2014Publication date: October 23, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Yi WU, Wei-Yueh SUNG, Pao-Huei CHANG CHIEN, Chi-Chih CHU, Cheng-Yin LEE, Gwo-Liang WENG
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Publication number: 20130161816Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.Type: ApplicationFiled: February 22, 2013Publication date: June 27, 2013Inventors: Chi-Chih Chu, Cheng-Yi Weng
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Patent number: 8446546Abstract: A backlight module and a display panel device using the same are provided. The backlight module includes a light source module, an open frame, and a reflector sheet. The open frame is disposed around the light source module and has a first free-end and a second free-end. A space interval exists between the first and second free-ends. The reflector sheet is disposed on a rear side of the light source module and has a body and a sidewall. The sidewall corresponds to the space interval between the first and second free-ends and extends over the light source module. The display panel further includes a liquid crystal display panel (LCD panel) on the light source module and a front frame which is disposed on the LCD panel enclosing a lateral side of the LCD panel. The sidewall of the reflector sheet extends between the lateral side of the LCD panel and the front frame to provide insulation.Type: GrantFiled: April 1, 2009Date of Patent: May 21, 2013Assignee: Au Optronics CorporationInventors: Ya-Ting Ho, Chi-Chih Chu, Keng-Ju Liu
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Patent number: 8405212Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.Type: GrantFiled: June 18, 2010Date of Patent: March 26, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih Chu, Cheng-Yi Weng
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Patent number: 8198131Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.Type: GrantFiled: July 29, 2010Date of Patent: June 12, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yi Weng, Chi-Chih Chu, Chien-Yuan Tseng
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Publication number: 20120049338Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Inventors: Kuang-Hsiung Chen, Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Hui-Shan Chang, Pei-Yu Hsu, Fa-Hao Wu, Chen-Yu Chia, Chi-Chih Chu, Cheng-Yi Weng, Ya-Wen Hsu
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Patent number: 8076765Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.Type: GrantFiled: July 22, 2009Date of Patent: December 13, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuang-Hsiung Chen, Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Hui-Shan Chang, Pei-Yu Hsu, Fa-Hao Wu, Chen-Yu Chia, Chi-Chih Chu, Cheng-Yi Weng, Ya-Wen Hsu
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Patent number: 8012797Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.Type: GrantFiled: August 25, 2009Date of Patent: September 6, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Chi-Chih Chu, Cheng-Yi Weng
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Publication number: 20110156251Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.Type: ApplicationFiled: June 18, 2010Publication date: June 30, 2011Inventors: Chi-Chih Chu, Cheng-Yi Weng
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Publication number: 20110117700Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.Type: ApplicationFiled: July 29, 2010Publication date: May 19, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: CHENG-YI WENG, Chi-Chih Chu, Chien-Yuan Tseng
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Patent number: 7866874Abstract: The present invention discloses a backlight module having replaceable light apparatus. The backlight module includes the replaceable light apparatus, a back plate and a frame body. The replaceable light apparatus includes a light control circuit, a securing device and conducting wires. The light control circuit is adapted to a frame body and a back plate of the backlight module. Additionally, the light control circuit has a plurality of light sources, a first end portion and a second end portion. The securing device has a supporting housing which has a position protrusion and a clamping portion for supporting the first end portion of the light control circuit along a first direction (X) and a third direction (Z). The clamping portion clamps the first end portion of the light control circuit along a second direction (Y) and the third direction (Z).Type: GrantFiled: July 22, 2008Date of Patent: January 11, 2011Assignee: AU Optronics Corp.Inventors: Keng-ju Liu, Wen-yuan Cheng, Chi-chih Chu
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Publication number: 20100237490Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a packaging substrate, a chip, an interposer substrate, a wire and an adhesive layer. The packaging substrate has an upper packaging surface. The chip is disposed on the upper packaging surface. The wire connects the packaging substrate and the interposer substrate. The adhesive layer is disposed between the packaging substrate and the interposer substrate, and covers the entire chip and part of the upper packaging surface. The adhesive layer includes a first adhesive part and a second adhesive part. The first adhesive part adheres the interposer substrate and the chip. The second adhesive part surrounds the first adhesive part, adheres the interposer substrate and the packaging substrate, and supports a periphery of the interposer substrate.Type: ApplicationFiled: September 17, 2009Publication date: September 23, 2010Inventors: Chi-Chih CHU, Lin-Wang YU
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Publication number: 20100171205Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.Type: ApplicationFiled: July 22, 2009Publication date: July 8, 2010Inventors: Kuang-Hsiung CHEN, Chi-Chih SHEN, Jen-Chuan CHEN, Wen-Hsiung CHANG, Hui-Shan CHANG, Pei-Yu HSU, Fa-Hao WU, Chen-Yu CHIA, Chi-Chih CHU, Cheng-Yi WENG, Ya-Wen HSU
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Publication number: 20100171207Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.Type: ApplicationFiled: August 25, 2009Publication date: July 8, 2010Inventors: Chi-Chih Shen, Jen-Chuan CHEN, Wen-Hsiung CHANG, Chi-Chih CHU, Cheng-Yi WENG
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Publication number: 20100171206Abstract: A semiconductor package includes: (1) a substrate including an upper surface and a lower surface opposite to the upper surface; (2) a chip mounted and electrically connected to the upper surface of the substrate; (3) an interposer mounted on the chip and electrically connected to the upper surface of the substrate, the interposer including an upper surface and a lower surface that is opposite to the upper surface and facing the chip, the interposer including a plurality of electrical contacts located on the upper surface of the interposer; and (4) a molding compound sealing the substrate, the interposer, and the chip, and exposing the lower surface of the substrate, the molding compound defining a plurality of holes that enclose and expose respective ones of the electrical contacts.Type: ApplicationFiled: August 20, 2009Publication date: July 8, 2010Inventors: Chi-Chih Chu, Cheng-Yi Weng
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Publication number: 20100014015Abstract: A backlight module and a display panel device using the same are provided. The backlight module includes a light source module, an open frame, and a reflector sheet. The open frame is disposed around the light source module and has a first free-end and a second free-end. A space interval exists between the first and second free-ends. The reflector sheet is disposed on a rear side of the light source module and has a body and a sidewall. The sidewall corresponds to the space interval between the first and second free-ends and extends over the light source module. The display panel further includes a liquid crystal display panel (LCD panel) on the light source module and a front frame which is disposed on the LCD panel enclosing a lateral side of the LCD panel. The sidewall of the reflector sheet extends between the lateral side of the LCD panel and the front frame to provide insulation.Type: ApplicationFiled: April 1, 2009Publication date: January 21, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Ya-Ting Ho, Chi-Chih Chu, Keng-Ju Liu
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Patent number: 7642133Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.Type: GrantFiled: July 26, 2007Date of Patent: January 5, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Yi Wu, Wei-Yueh Sung, Pao-Huei Chang Chien, Chi-Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng
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Publication number: 20090290381Abstract: The present invention discloses a backlight module having replaceable light apparatus. The backlight module includes the replaceable light apparatus, a back plate and a frame body. The replaceable light apparatus includes a light control circuit, a securing device and conducting wires. The light control circuit is adapted to a frame body and a back plate of the backlight module. Additionally, the light control circuit has a plurality of light sources, a first end portion and a second end portion. The securing device has a supporting housing which has a position protrusion and a clamping portion for supporting the first end portion of the light control circuit along a first direction (X) and a third direction (Z). The clamping portion clamps the first end portion of the light control circuit along a second direction (Y) and the third direction (Z).Type: ApplicationFiled: July 22, 2008Publication date: November 26, 2009Applicant: AU Optronics Corp.Inventors: Keng-ju Liu, Wen-yuan Cheng, Chi-chih Chu
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Patent number: 7473629Abstract: A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.Type: GrantFiled: December 6, 2006Date of Patent: January 6, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Chang Tai, Chi-Chih Chu, Meng-Jung Chuang, Cheng-Yin Lee, Yao-Ting Huang, Kuang-Lin Lo
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Patent number: 7439619Abstract: The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.Type: GrantFiled: January 3, 2005Date of Patent: October 21, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Chih Chu, Gwo-Liang Weng, Shih-Chang Lee