Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

Abstract: A semiconductor wafer processing system includes a stocker having an interior surface, a wafer carrier disposed within the stocker, a wafer shelf disposed within the wafer carrier for storing a semiconductor wafer, and a discharge circuit including a first conductor electrically coupled to the wafer shelf and a first current controller electrically coupled to the first conductor and to the interior surface of the stocker.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.

Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.