Patents by Inventor Chi Fan

Chi Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137599
    Abstract: A terminal, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: receiving an object in a live streaming; displaying the object on the terminal; detecting a keyword in the object corresponding to a function in the live streaming; and triggering the function in response to an operation on the object. The present disclosure may allow the streamers to generate or amend an object such as stickers on the live streaming room in a more flexible manner. At the same time, the viewer may perform an operation on the object to realize a corresponding function in a more convenient manner. Therefore, the interaction among streamers and viewers may be increased, and the user experience may also be enhanced.
    Type: Application
    Filed: July 2, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Cheng FAN, Sz-Chi HUANG, Chih-Yuan WANG
  • Patent number: 11966133
    Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: April 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
  • Patent number: 11961779
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 11955962
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. A plurality of non-dissipative elements may be connected in parallel or in series between the first pair of switches and the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. The defined sequence may have a switching pattern with a voltage change portion arranged to cause a change in an output voltage of the capacitive element driver during application thereof on the capacitive element driver.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: April 9, 2024
    Assignee: NEOLITH LLC
    Inventors: Tsz Yin Man, Chi Fan Yung, Bruce C. Larson
  • Publication number: 20240103746
    Abstract: An apparatus comprises a processing device configured to receive a request to store data on a storage system, and to determine storage node correlation metrics for storage nodes of the storage system characterizing probabilities of input/output operations being directed to filesystems having data stored on the storage nodes. The processing device is also configured to select, based on the storage node correlation metrics, one of the storage nodes to utilize for storing a given portion of the data, and to determine storage device correlation metrics for storage devices of the selected storage node characterizing probabilities of input/output operations being directed to filesystems having data stored on the storage devices. The processing device is further configured to select, based on the storage device correlation metrics, one of the storage devices of the selected storage node to utilize for storing the given data portion.
    Type: Application
    Filed: October 12, 2022
    Publication date: March 28, 2024
    Inventors: Huijuan Fan, Chi Chen, Hailan Dong
  • Publication number: 20240096800
    Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
  • Publication number: 20240096769
    Abstract: The disclosure provides a method for manufacturing a semiconductor package assembly, which results in a semiconductor package assembly with a more even distributed stress concentrations, reduced solder crack occurrences and limited solder filler joint connections.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Haibo Fan, Zhou Zhou, Chi Ho Leung
  • Publication number: 20240072158
    Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
  • Patent number: 11914875
    Abstract: An apparatus comprises a processing device configured to identify storage workloads to be run on a storage system, and to determine a mix of input/output (TO) patterns associated with the identified storage workloads, the mix of IO patterns comprising a first set of IO patterns characterizing types of IO operations performed by a first storage workload and at least a second set of IO patterns characterizing types of IO operations performed by a second storage workload. The processing device is also configured to calculate an affinity metric for the mix of IO patterns, the calculated affinity metric characterizing a difference between (i) performance metrics for the mix of IO patterns running concurrently and (ii) the first and second sets of IO patterns running individually. The processing device is further configured to allocate the identified storage workloads to storage devices of the storage system based on the calculated affinity metric.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Chi Chen, Hailan Dong, Huijuan Fan
  • Publication number: 20240026362
    Abstract: Provided are interfering RNAs (e.g., siRNAs) targeting SARS-CoV (e.g., the POL, Spike, Helicase, or Envelop gene thereof) and therapeutic uses thereof for inhibiting SARS-CoV infection and/or treating diseases associated with the infection (e.g., COVID-19).
    Type: Application
    Filed: December 3, 2021
    Publication date: January 25, 2024
    Applicants: MICROBIO (SHANGHAI) CO. LTD., ONENESS BIOTECH CO. LTD.
    Inventors: Yi-Chung CHANG, Chi-Fan YANG, Yi-Fen CHEN, Chia-Chun YANG, Yuan-Lin CHOU
  • Publication number: 20230292525
    Abstract: A device structure according to the present disclosure includes a conductive feature disposed in a first dielectric layer, a ferroelectric tunnel junction (FTJ) stack disposed over the conductive feature, a spacer disposed along sidewalls of the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, and a contact via extending through the second dielectric layer. The FTJ stack includes a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer over the bottom electrode layer, and a top electrode layer on the ferroelectric layer. The top electrode layer is formed of a conductive metal oxide.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 14, 2023
    Inventors: Chien Ta Huang, Chia Chi Fan, Chun-Yang Tsai, Kuo-Ching Huang, Harry-Haklay Chuang
  • Publication number: 20230231553
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. A plurality of non-dissipative elements may be connected in parallel or in series between the first pair of switches and the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. The defined sequence may have a switching pattern with a voltage change portion arranged to cause a change in an output voltage of the capacitive element driver during application thereof on the capacitive element driver.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 20, 2023
    Inventors: Tsz Yin MAN, Chi Fan YUNG, Bruce C. LARSON
  • Patent number: 11693492
    Abstract: A mouse is provided. The mouse includes a casing, a circuit board, a micro switch base, and a micro switch. The casing includes a button. The circuit board is disposed in the casing. The micro switch base is disposed on the circuit board, and includes a plurality of first openings and a plurality of second openings. The micro switch is fixed on the micro switch base through at least one of the first openings, and electrically connected to the circuit board through the first openings or the second openings.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 4, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chi-Fan Chen, Yi-Chung Chiu, Chen-Hou Lo
  • Publication number: 20230204558
    Abstract: A water quality monitoring device and a monitoring method thereof are provided. The water quality monitoring device includes a water tank, a first and a second optical detection devices and a control circuit. The water tank has an accommodating space to carry a liquid. The first optical detection device provides a first light to detect and obtain a first reference light intensity, a first scattered light intensity, and a first penetrating light intensity. The second optical detection device provides a second light to detect and obtain a second reference light intensity, a second scattered light intensity, and a second penetrating light intensity. The control circuit calculates a water quality detection value of the liquid based on the first reference light intensity, the first scattered light intensity, the first penetrating light intensity, the second reference light intensity, the second scattered light intensity, and the second penetrating light intensity.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Chen-Hua Chu, Chun-Kuo Liu, Yi-Hong Liu, Chi-Fan Wang, Jung-Hao Wang, Sheng-Wei Peng, Yu-Xuan Lin
  • Publication number: 20230110159
    Abstract: A light emitting device includes a substrate, multiple light emitting diodes disposed on the substrate and a light-reflecting resist. The light emitting diode has a first electrode and a second electrode, both of which are disposed on a first surface of the light emitting diode facing the substrate. The light-reflecting resist is disposed between the light emitting diodes and directly contacts a side surface of the light emitting diode. At least a portion of the light-reflecting resist is disposed between the first electrode and the second electrode.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 13, 2023
    Inventors: Chun-Hsiang CHAN, Seok-Lyul LEE, Shih-Chi FAN JIANG, Li-Kai CHIA
  • Patent number: 11575376
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 7, 2023
    Assignee: NEOLITH LLC
    Inventors: Tsz Yin Man, Chi Fan Yung, Bruce C. Larson
  • Publication number: 20220365615
    Abstract: An on-cell touch display and a preparing method thereof are provided. The on-cell touch display includes a display panel and a touch sensor disposed on the display panel. The touch sensor includes a first conductive thin film, which is formed on the display panel; an insulating layer, which is formed on the first conductive thin film; a second conductive thin film, which is formed on the insulating layer; and a protective film, which is formed on the second conductive thin film; wherein the non-uniformity value of the first conductive thin film and the second conductive thin film is less than 15% respectively.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: Chung-Chin Hsiao, Siou-Cheng Lien, Chia-Yang Tsai, Chi-Fan Hsiao
  • Patent number: 11494040
    Abstract: A stacking structure includes a substrate, a silver nanowire layer provided on a top of the substrate, and a metal layer provided on a top of the silver nanowire layer. The silver nanowire layer includes a plurality of silver nanowires and an indium tin oxide (ITO) covered on the plurality of silver nanowires. The silver nanowire layer has an overall thickness that is 2.35 to 24 times as thick as a thickness of the ITO. A touch sensor including the above described stacking structure is also disclosed.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: November 8, 2022
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Chung-Chin Hsiao, Siou-Cheng Lien, Yi-Wen Chiu, Chi-Fan Hsiao
  • Patent number: D967181
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 18, 2022
    Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., Ltd
    Inventors: Chi-Fan Lin, Ying-Wei Sheng
  • Patent number: D1004616
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., Ltd
    Inventors: Ying-Wei Sheng, Ping-Hao Liu, Chi-Fan Lin, Qiang Yu, Wei-Chien Hsu, Jin-Jin Zou