Abstract: The present invention provides a panorama image capturing device and a panorama image capturing module thereof. The panorama image capturing module includes a lens structure, an optical structure, a single image sensing chip, and a single image signal processor. The lens structure includes a first lens assembly for capturing a first predetermined image light source, and a second lens assembly for capturing a second predetermined image light source. The optical structure is disposed between the first lens assembly and the second lens assembly. The single image sensing chip has a first image sensing region for receiving the first predetermined image light source through the optical structure, and a second image sensing region for receiving the second predetermined image light source through the optical structure. The first and the second predetermined image light sources are processed by the single image signal processor for obtaining a panorama image.

Abstract: An input apparatus and method for use in an information input unit. The information input unit is coupled to an information device having a display. The input apparatus includes an operational selection module, which is coupled to the information input unit, for generating a press signal in response to a pressing operation detected by the operational selection module and for generating a shift signal in response to a shifting operation detected by the operational selection module. A control chip of the information input unit activates the information device to display a graphical interface indicative of a set of options on the display when the information input unit receives the shift signal. Selection of the set of options on the graphical interface is made according to the press signal and the shift signal.

Abstract: A computer system cache memory has a caching tag which stores a subset of the L2 cache memory tag store. The caching tag is smaller, faster memory device than the L2 cache memory. The cache memory latency is reduced because the tag access time and tag comparison time are improved due to the caching tag. The caching tag may be manufactured to be located on the same chip as the cache controller, which allows faster data access than if the caching tag is located on a separate chip.