Patents by Inventor Chih-An Yang
Chih-An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178005Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Piao CHUU, Ming-Yang LI, Lain-Jong LI
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Patent number: 11996468Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.Type: GrantFiled: September 2, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chih Lin, Hsiu-Hao Tsao, Szu-Chi Yang, Shih-Hao Lin, Yu-Jiun Peng, Chang-Jhih Syu, An Chyi Wei
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Patent number: 11996165Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.Type: GrantFiled: May 17, 2022Date of Patent: May 28, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
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Publication number: 20240170415Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.Type: ApplicationFiled: April 11, 2023Publication date: May 23, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
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Patent number: 11990430Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.Type: GrantFiled: February 26, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
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Patent number: 11990537Abstract: A heterojunction bipolar transistor includes: a substrate; a base mesa disposed on the substrate, wherein the base mesa includes a collector layer and a base layer disposed on the collector layer, and wherein in a top view, the base layer includes a first edge and a second edge opposite to the first edge; an emitter layer disposed on the base layer; a base electrode disposed on the substrate and connected to the base layer; a dielectric layer disposed on the base electrode, wherein a first via hole is formed in the dielectric layer at the first edge of the base layer, and a second via hole is formed in the dielectric layer at the second edge of the base layer; and a conductive feature disposed on the dielectric layer, wherein the conductive feature is connected to the base electrode through the first via hole and the second via hole.Type: GrantFiled: June 23, 2022Date of Patent: May 21, 2024Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chih-Yang Kao, Chien-Rong Yu
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Publication number: 20240161814Abstract: A non-volatile memory receives a supply voltage. The non-volatile memory includes a reference current generator and a sensing circuit. The reference current generator provides a reference current to the sensing circuit. The reference current generator includes a control voltage generation circuit, a current path selecting circuit and a mirroring circuit. The control voltage generation circuit receives a control signal and generates a control voltage according to the control signal. The current path selecting circuit generates the reference current. A current input terminal of the mirroring circuit receives the reference current. If the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage. If the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.Type: ApplicationFiled: November 9, 2023Publication date: May 16, 2024Inventors: Chih-Yang HUANG, Woan-Yun HSIAO
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Publication number: 20240156440Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: HAO-LI LIU, HSIANG-CHING LIN, ZHEN-YUAN LIAO, HSIANG-YANG MA, CHIH-HUNG TSAI, CHUN-HAO CHEN
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Patent number: 11983479Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.Type: GrantFiled: August 10, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
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Publication number: 20240152288Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.Type: ApplicationFiled: January 15, 2024Publication date: May 9, 2024Applicant: Silicon Motion, Inc.Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
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Publication number: 20240155292Abstract: An electronic device includes two speakers, a single functional chip, a parameter extraction circuit, an audio processing module, a gain adjusting circuit and a current detecting unit. The current detecting unit is disposed in the functional chip for detecting the driving current of the two speakers. The functional chip provides the driving voltage of the two speakers based on an output signal and converts the analogue current/voltages of the two speakers into digital current/voltages. The parameter extraction circuit acquires the parameter of each speaker based on the digital current/voltages. The audio processing module acquires the gains of various physical quantities based on the parameter of each speaker and determines the final gain of each physical quantity. The gain adjusting circuit provides the output signal by adjusting the gain of an input signal based on the final gain of each physical quantity.Type: ApplicationFiled: December 12, 2022Publication date: May 9, 2024Applicant: RICHTEK TECHNOLOGY CORP.Inventors: Tsung-Han Yang, Yen-Chih Wang, Ming-Jun Hsiao, Tsung-Nan Wu
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Publication number: 20240149315Abstract: The present invention discloses a microwave heating system for desorbing contaminated soil, comprising: a feeding module; a heating cavity; a first microwave suppression cavity; a second microwave suppression cavity; a conveyor belt; a feeding device; and an exhaust module. The feeding device is arranged above the first microwave suppression cavity or the second microwave suppression cavity, and the feeding device contains a microwave absorber material. The invention further discloses a microwave heating process for desorption of polluted soil. With the microwave heating system and process for desorbing contaminated soil, the contaminated soil can be heated quickly and uniformly, and quickly cooled and taken out smoothly.Type: ApplicationFiled: September 7, 2023Publication date: May 9, 2024Inventors: Tsung-Chih YU, Tung-Chieh YANG, Wu-Yeh LEE, Min-Hang WENG
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Publication number: 20240145600Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih WEN, Yi-Lin YANG, Hai-Ching CHEN
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Publication number: 20240145403Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.Type: ApplicationFiled: February 6, 2023Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
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Publication number: 20240144708Abstract: An examination system is provided. The examination system includes an optical detector and analyzer. The optical detector emits a detection light source toward a target object and detects a respondent light which is induced from the target object in response to the detection light source to generate image data. The image data indicates a detection image. The analyzer receives the image data and determines which region of the target object the detection image belongs to according to the image data. When the analyzer determines that the detection image belongs to a specific region of the target object, the analyzer extracts at least one feature of the image data to serve as a basis for classification of the specific region.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Chih-Yang CHEN, Pau-Choo CHUNG CHAN, Sheng-Hao TSENG
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Publication number: 20240139301Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.Type: ApplicationFiled: November 19, 2021Publication date: May 2, 2024Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
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Patent number: 11969815Abstract: An automatic material changing and welding system for stamping materials includes a welding transfer sliding table and a welding platform. The automatic material changing device further includes a feeding system. The feeding system includes a double-head uncoiling machine, an automatic feeding machine and a flattening machine. The automatic material changing device is used for automatic feeding for a stamping machine. The system triggers a material changing signal through a sensor to control and integrate the welding transfer sliding table and the welding platform to act to execute a welding procedure, so that the stamping materials are in welding connection with new and old coiled materials through a welding connection plate to realize continuous production operation of an automated stamping production line.Type: GrantFiled: December 28, 2021Date of Patent: April 30, 2024Assignee: NATIONAL KAOHSIUNG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Chun-Chih Kuo, Hao-Lun Huang, Bor-Tsuen Lin, Cheng-Yu Yang
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Publication number: 20240136117Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.Type: ApplicationFiled: October 1, 2023Publication date: April 25, 2024Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
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Patent number: 11967642Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.Type: GrantFiled: September 3, 2021Date of Patent: April 23, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Yen Chen, Tuan-Wei Wang, Franky Juanda Lumbantoruan, Chun-Yang Chen
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Patent number: D1026913Type: GrantFiled: June 17, 2022Date of Patent: May 14, 2024Assignee: PRIMAX ELECTRONICS LTD.Inventors: Wen-Chih Chu, Cheng-Yen Yang