Patents by Inventor Chi-Heng Lin
Chi-Heng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240145412Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.Type: ApplicationFiled: November 27, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Huang, Chao-Ting Chen, Jui-Fa Lu, Chi-Heng Lin
-
Patent number: 11942556Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.Type: GrantFiled: April 8, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ru Lin, Shu-Han Chen, Yi-Shao Li, Chun-Heng Chen, Chi On Chui
-
Publication number: 20240088156Abstract: A semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the at least one fin. The second dielectric layer between the at least one fin and the first dielectric layer. A thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui
-
Patent number: 11609559Abstract: A data processing system, including a cyclic correlation establishing module, a data pattern establishing module, and a data pattern alignment module, is provided. The cyclic correlation establishing module receives a plurality of first sensor data, obtained from a first sensor operation performed on processing devices, and receives a table of processing steps and cyclic procedures. The cyclic correlation establishing module obtains a data correlation of the first sensor data according to the number of sample points in a data cycle of the first sensor data and the table to correct the first sensor data. The data pattern establishing module obtains a plurality of first data pattern features from the first sensor data. The data pattern alignment module aligns a plurality of second sensor data obtained from a second sensor operation performed on the processing devices with the first sensor data according to the first data pattern features.Type: GrantFiled: May 14, 2020Date of Patent: March 21, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsin-Chi Chen, Chuang-Hua Chueh, Chun-Fang Chen, Chi-Heng Lin, Chun-Hsu Chen
-
Publication number: 20210200196Abstract: A data processing system, including a cyclic correlation establishing module, a data pattern establishing module, and a data pattern alignment module, is provided. The cyclic correlation establishing module receives a plurality of first sensor data, obtained from a first sensor operation performed on processing devices, and receives a table of processing steps and cyclic procedures. The cyclic correlation establishing module obtains a data correlation of the first sensor data according to the number of sample points in a data cycle of the first sensor data and the table to correct the first sensor data. The data pattern establishing module obtains a plurality of first data pattern features from the first sensor data. The data pattern alignment module aligns a plurality of second sensor data obtained from a second sensor operation performed on the processing devices with the first sensor data according to the first data pattern features.Type: ApplicationFiled: May 14, 2020Publication date: July 1, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsin-Chi CHEN, Chuang-Hua CHUEH, Chun-Fang CHEN, Chi-Heng LIN, Chun-Hsu Chen
-
Publication number: 20150104914Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between ?40° C. and ?120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
-
Patent number: 8835240Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.Type: GrantFiled: March 5, 2012Date of Patent: September 16, 2014Assignee: United Microelectronics CorporationInventors: An-Chi Liu, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
-
Publication number: 20130337622Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
-
Patent number: 8536072Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: GrantFiled: February 7, 2012Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
-
Publication number: 20130230989Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: United Microelectronics CorporationInventors: An-Chi LIU, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
-
Publication number: 20130203226Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li