Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: The present invention relates to a microelectrode, a microelectrode array, and a method of manufacturing the microelectrode of which temperature can be controlled. The microelectrode comprises a sealed cavity formed in a silicon substrate for thermal isolation, a microheater formed on the sealed cavity, and an electrode heated indirectly by the microheater. According to the present invention, it is possible to manufacture with CMOS process the microelectrode and the microelectrode array which have excellent electric insulation and thermal isolation between a microheater and a silicon substrate, which has a small power consumption, which has high heating and cooling speed and which has no corrosion.

Abstract: The present invention relates to a micro electro mechanical system (MEMS); and, more particularly, to a micro pump used in micro fluid transportation and control and a method for fabricating the same. The micro pump according to the present invention comprises: trenches formed in a silicon substrate in order to form a pumping region including a main pumping region and an auxiliary pumping region; channels formed on both sides of the pumping region; a flow prevention region having backward-flow preventing layers to resist a fluid flow; inlet/outlet regions formed at each of the channels which are disposed on both ends of the pumping region; an outer layer covering the trenches of the silicon substrate and opening portions of the inlet/outlet regions; and a thermal conducting layer formed on the outer layer and over the main pumping region so that a pressure of the fluid in the main pumping region is increased by the thermal conducting layer.

Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: The present invention relates to a micro electro mechanical system (MEMS); and, more particularly, to a micro pump used in micro fluid transportation and control and a method for fabricating the same. The micro pump according to the present invention comprises: trenches formed in a silicon substrate in order to form a pumping region including a main pumping region and an auxiliary pumping region; channels formed on both sides of the pumping region; a flow prevention region having backward-flow preventing layers to resist a fluid flow; inlet/outlet regions formed at each of the channels which are disposed on both ends of the pumping region; an outer layer covering the trenches of the silicon substrate and opening portions of the inlet/outlet regions; and a thermal conducting layer formed on the outer layer and over the main pumping region so that a pressure of the fluid in the main pumping region is increased by the thermal conducting layer.

Abstract: Disclosed is a a method of fabricating a MEMS device by means of surface micromachining without leaving any stiction or residues by etching silicon oxide of a sacrificial layer, which is an intermediate layer between a substrate and a microstructure, rather than by etching silicon oxide of a semiconductor device. The method according to the invention includes the steps of supplying alcohol vapor bubbled with anhydrous HF, maintaining a temperature of the supplying device and a moving path of the anhydrous HF and the alcohol to be higher than a boiling point of the alcohol, performing a vapor etching by controlling a temperature and a pressure to be within the vapor region of a phase equilibrium diagram of water, and removing silicon oxide of a sacrificial layer on a lower portion of the microstructure.

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract: A chemical vapor deposition apparatus and a copper film formation method are disclosed. The chemical vapor deposition apparatus includes a process gas delivery unit including a first storing unit using a liquid deposition source, a delivery unit for transferring a liquid deposition source in the first storing unit to an evaporator, and an evaporator for vaporizing the liquid deposition source transferred from the delivery unit and supplying a process gas; and a reaction chamber for receiving the process gas from the process gas delivery unit and deposition a predetermined thin film on a wafer or substrate mounted therein.

Abstract: An improved method for forming diffusion barrier layers for sub-micron connects in integrated circuits is disclosed. The dual diffusion barriers is easily formed according to two-step annealing processes. The anneal includes two anneal cycles or steps, each cycle is performed at a separate and distinct temperature cycles. Each cycle is performed in the presence of ammonia (NH3) or nitrogen ambient. As a result of the first low-temperature cycle, a nitridation occurs at the upper surface to form a binary diffusion barrier layer. As a result of the second high-temperature cycle, an out-diffusion of silicon ions occurs at the lower surface to form a ternary alloys. The dual diffusion barriers obtained by a simple and easy two-step anneal processing exhibits an improved barrier performance. Furthermore, it is possible to form highly stable multilevel interconnections without any deterioration problems by reducing the sophisticated processing steps.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: The present invention relates to a method for forming a diffusion barrier layer, the method comprising the steps of: forming an insulation membrane having an opening for exposing a diffusion region to a silicon substrate formed with the diffusion region of a predetermined conductivity; vacuum-evaporating a metal of high melting point to surface and sides of the insulation membrane and to an upper area of the diffusion region, to thereby form a metal layer; and forming on the metal layer a low resistance layer and a diffusion barrier layer according to first and second quick heating treatment steps under nitric or ammoniac atmosphere. Accordingly, the low resistance layer can be thinned out while the diffusion prevention layer can be quickly formed to thereby improve diffusion prevention characteristic and to reduce stress from an interface with the semiconductor substrate.